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/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
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/freebsd/sys/contrib/device-tree/src/riscv/kendryte/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/k210-clk.h>
10 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13 #address-cells = <1>;
14 #size-cells = <1>;
23 * Since this is a non-ratified draft specification, the kernel does not
28 #address-cells = <1>;
29 #size-cells = <0>;
30 timebase-frequency = <7800000>;
34 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp1 //===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
26 "riscv-v-register-bit-width-lmul",
33 "riscv-v-slp-max-vf",
48 InstructionCost LMULCost = TLI->getLMULCost(VT); in getRISCVInstructionCost()
54 case RISCV::VRGATHER_VI: in getRISCVInstructionCost()
55 Cost += TLI->getVRGatherVICost(VT); in getRISCVInstructionCost()
57 case RISCV::VRGATHER_VV: in getRISCVInstructionCost()
58 Cost += TLI->getVRGatherVVCost(VT); in getRISCVInstructionCost()
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H A DRISCVISelDAGToDAG.cpp1 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISC-V -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines an instruction selector for the RISC-V target.
11 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "riscv-isel"
29 #define PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection"
32 "riscv-use-rematerializable-movimm", cl::Hidden,
37 namespace llvm::RISCV { namespace
47 } // namespace llvm::RISCV
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H A DRISCVAsmPrinter.cpp1 //===-- RISCVAsmPrinter.cpp - RISC-V LLVM assembly writer -----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // of machine-dependent LLVM code to the RISC-V assembly language.
12 //===----------------------------------------------------------------------===//
19 #include "RISCV.h"
47 #define DEBUG_TYPE "asm-printer"
50 "Number of RISC-V Compressed instructions emitted");
53 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
65 StringRef getPassName() const override { return "RISC-V Assembly Printer"; } in getPassName()
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H A DRISCVISelLowering.cpp1 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation ------
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H A DRISCVInstrInfo.cpp1 //===-- RISCVInstrInfo.cpp - RISC-V Instruction Information -----*-
70 namespace llvm::RISCV { global() namespace
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H A DRISCVGatherScatterLowering.cpp1 //===- RISCVGatherScatterLowering.cpp - Gather/Scatter lowering -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // RISC-V intrinsics.
12 //===----------------------------------------------------------------------===//
14 #include "RISCV.h"
32 #define DEBUG_TYPE "riscv-gather-scatter-lowering"
63 return "RISC-V gather/scatter lowering"; in getPassName()
83 "RISC-V gather/scatter lowering pass", false, false)
91 if (!isa<FixedVectorType>(StartC->getType())) in matchStridedConstant()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DRISCVAttributes.h1 //===-- RISCVAttributes.h - RISCV Attributes --------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains enumerations for RISCV attributes as defined in RISC-V
12 // RISC-V ELF psABI specification
14 // https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
16 //===----------------------------------------------------------------------===//
28 // Attribute types in ELF/.riscv.attributes.
41 …// https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomi…
/freebsd/sys/riscv/riscv/
H A Didentcpu.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
11 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
63 const char machine[] = "riscv";
75 /* Supervisor-mode extension support. */
84 u_int isa_extensions; /* Single-letter extensions. */
97 * Micro-architecture tables.
104 #define MARCHID_END { -1ul, NULL }
106 /* Open-source RISC-V architecture IDs; globally allocated. */
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/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Driscv,pmu.yaml1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-
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/freebsd/sys/contrib/device-tree/Bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/freebsd/contrib/llvm-project/clang/lib/Basic/Targets/
H A DRISCV.cpp1 //===--- RISCV.cpp - Implement RISC-V target feature support --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements RISC-V TargetInfo objects.
11 //===----------------------------------------------------------------------===//
13 #include "RISCV.h"
26 // clang-format off in getGCCRegNames()
49 // clang-format on in getGCCRegNames()
80 // A 12-bit signed immediate. in validateAsmConstraint()
81 Info.setRequiresImmediate(-2048, 2047); in validateAsmConstraint()
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/freebsd/sys/contrib/device-tree/src/riscv/canaan/
H A Dk210.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h>
12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
15 #address-cells = <1>;
16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210";
21 * Since this is a non-ratified draft specification, the kernel does not
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/freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/
H A DFlang.cpp1 //===-- Flang.cpp - Flang+LLVM ToolChain Implementations --------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 #include "Arch/RISCV.h"
29 /// Add -x lang to \p CmdArgs for \p Input.
32 CmdArgs.push_back("-x"); in addDashXForInput()
72 /// -Ofast, -O4, -O<number> and -f[no-]version-loops-for-stride.
74 /// -fno-version-loops-for-stride.
76 /// -floop-versioning
77 /// -Ofast
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp1 //===-- RISCVInstructionSelector.cpp -----------------------------*- C++ -*-==//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// RISC-V.
12 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "riscv-isel"
55 // tblgen-erated 'select' implementation, used as the initial selector for
124 // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel
165 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectShiftMask()
181 // instructions as well as 32-bit ones): in selectShiftMask()
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/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A DRISCVISAInfo.cpp1 //===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ----------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
84 outs() << "All available -march extensions for RISC-V\n\n"; in printSupportedExtensions()
103 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printSupportedExtensions()
114 outs() << "\nUse -march to specify the target's extension.\n" in printSupportedExtensions()
115 "For example, clang -march=rv32i_v1p0\n"; in printSupportedExtensions()
121 outs() << "Extensions enabled for the given RISC-V target\n\n"; in printEnabledExtensions()
141 if (EnabledFeatureNames.count("experimental-" + Name.str()) != 0) { in printEnabledExtensions()
149 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printEnabledExtensions()
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/freebsd/stand/
H A Ddefs.mk24 # CPUTYPE?=native prevent that, and introduce an endless game of whack-a-mole
29 .if ${LDFLAGS:M-nostdlib}
44 # built 32-bit and some 64-bit (lib*, efi). Centralize all the 32-bit magic here
84 CFLAGS+= -nostdinc
87 # the only thing that should be there are -I directives, and as few of
91 CFLAGS+= -I${BOOTOBJ}/libsa32
93 CFLAGS+= -I${BOOTOBJ}/libsa
95 CFLAGS+= -I${SASRC} -D_STANDALONE
96 CFLAGS+= -I${SYSDIR}
98 CFLAGS+= -Ddouble=jagged-little-pill -Dfloat=floaty-mcfloatface
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H A Dloader.mk3 CFLAGS+=-I${LDRSRC}
10 CFLAGS.module.c += -I$(SRCTOP)/sys/teken -I${SRCTOP}/contrib/pnglite
13 CFLAGS.pnglite.c+= -I${SRCTOP}/contrib/pnglite
14 CFLAGS.pnglite.c+= -DHAVE_MEMCPY -I${SRCTOP}/sys/contrib/zlib
27 .elif ${MACHINE_CPUARCH} == "riscv"
40 # non-default values won't work due to buggy support for that component being
60 CFLAGS.part.c+= -DHAVE_MEMCPY -I${SRCTOP}/sys/contrib/zlib
73 CFLAGS+= -DMD_IMAGE_SIZE=${MD_IMAGE_SIZE}
79 # Machine-independent ISA PnP
92 CFLAGS.interp_lua.c= -DLUA_PATH=\"${LUAPATH}\" -I${FLUASRC}/modules
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/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DELF.h1 //===- llvm/BinaryFormat/ELF.h - ELF constants and structures ---*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This header contains common, non-processor-specific data structures and
14 // Version 1.2, May 1995. The ELF64 stuff is based on ELF-64 Object File Format
17 //===----------------------------------------------------------------------===//
70 Elf32_Word e_flags; // Processor-specific flags
86 // 64-bit ELF header. Fields are the same as for ELF32, but with different
121 ET_LOOS = 0xfe00, // Beginning of operating system-specific codes
122 ET_HIOS = 0xfeff, // Operating system-specific
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/freebsd/stand/efi/include/
H A Defiprot.h6 Copyright (c) 1999 - 2002 Intel Corporation. All rights reserved
27 --*/
636 // RISC-V EFI Boot Protocol
638 // https://github.com/riscv-non-isa/riscv-uefi
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp1 //===-- RISCVAsmParser.cpp - Parse RISC-V assembly to MCInst instructions -===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
47 #define DEBUG_TYPE "riscv-asm-parser"
50 "Number of RISC-V Compressed instructions emitted");
52 static cl::opt<bool> AddBuildAttributes("riscv-add-build-attributes",
56 extern const SubtargetFeatureKV RISCVFeatureKV[RISCV::NumSubtargetFeatures];
85 bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); } in isRV64()
86 bool isRVE() const { return getSTI().hasFeature(RISCV::FeatureStdExtE); } in isRVE()
88 return getSTI().hasFeature(RISCV::Experimental); in enableExperimentalExtension()
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/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DLoongArch.cpp1 //===- LoongArch.cpp ------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
75 // produces a PC-relative intermediate value with the lowest 12 bits zeroed (the
80 // Here a "page" is in fact just another way to refer to the 12-bit range
95 // (lu32i.d and lu52i.d). Compensate all the sign-extensions is a bit in getLoongArchPageDelta()
103 pcalau12i_pc = pc - 8; in getLoongArchPageDelta()
109 pcalau12i_pc = pc - 12; in getLoongArchPageDelta()
115 uint64_t result = getLoongArchPage(dest) - getLoongArchPage(pcalau12i_pc); in getLoongArchPageDelta()
117 result += 0x1000 - 0x1'0000'0000; in getLoongArchPageDelta()
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H A DRISCV.cpp1 //===- RISCV.cpp ----------------------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
30 class RISCV final : public TargetInfo { class
32 RISCV();
99 return (v & ((1ULL << (begin + 1)) - 1)) >> end; in extractBits()
110 RISCV::RISCV() { in RISCV() function in RISCV
115 if (config->is64) { in RISCV()
141 if (config->is64) in getEFlags()
142 return cast<ObjFile<ELF64LE>>(f)->getObj().getHeader().e_flags; in getEFlags()
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/freebsd/contrib/llvm-project/clang/lib/Sema/
H A DSemaLookup.cpp1 //===--------------------- SemaLookup.cpp - Name Lookup ------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements name lookup for C, C++, Objective-C, and
10 // Objective-C++.
12 //===----------------------------------------------------------------------===//
112 // both the using-directive and the nominated namespace. in visitScopeChain()
113 DeclContext *InnermostFileDC = InnermostFileScope->getEntity(); in visitScopeChain()
114 assert(InnermostFileDC && InnermostFileDC->isFileContext()); in visitScopeChain()
116 for (; S; S = S->getParent()) { in visitScopeChain()
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