riscv\-isa\-manual (full) in projects: freebsd

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Searched +full:riscv +full:- +full:isa +full:- +full:manual (Results 1 – 22 of 22) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/riscv/
H A D	extensions.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR MIT) 3 --- 4 $id: http://devicetree.org/schemas/riscv/extensions.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V ISA extensions 10 - Paul Walmsley <paul.walmsley@sifive.com> 11 - Palmer Dabbelt <palmer@sifive.com> 12 - Conor Dooley <conor@kernel.org> 15 RISC-V has a large number of extensions, some of which are "standard" 16 extensions, meaning they are ratified by RISC-V International, and others [all …]`
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A D	riscv,cpu-intc.yaml	1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC-V Hart-Level Interrupt Controller (HLIC) 10 RISC-V cores include Control Status Registers (CSRs) which are local to 11 each CPU core (HART in RISC-V terminology) and can be read or written by 16 The RISC-V supervisor ISA manual specifies three interrupt sources that are 19 cores. The timer interrupt comes from an architecturally mandated real- 22 the HLIC, which are routed via the platform-level interrupt controller [all …]
H A D	riscv,cpu-intc.txt	1 RISC-V Hart-Level Interrupt Controller (HLIC) 2 --------------------------------------------- 4 RISC-V cores include Control Status Registers (CSRs) which are local to each 5 CPU core (HART in RISC-V terminology) and can be read or written by software. 10 The RISC-V supervisor ISA manual specifies three interrupt sources that are 13 timer interrupt comes from an architecturally mandated real-time timer that is 16 via the platform-level interrupt controller (PLIC). 18 All RISC-V systems that conform to the supervisor ISA specification are 20 interrupt map is defined by the ISA it's not listed in the HLIC's device tree 27 - compatible : "riscv,cpu-intc" [all …]
H A D	sifive,plic-1.0.0.txt	1 SiFive Platform-Level Interrupt Controller (PLIC) 2 ------------------------------------------------- 4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller 5 (PLIC) high-level specification in the RISC-V Privileged Architecture 10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 13 Each interrupt can be enabled on per-context basis. Any context can claim 21 While the PLIC supports both edge-triggered and level-triggered interrupts, 23 specified in the PLIC device-tree binding. 25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the 26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that [all …]
H A D	sifive,plic-1.0.0.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 4 --- 5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: SiFive Platform-Level Interrupt Controller (PLIC) 11 SiFive SoCs and other RISC-V SoCs include an implementation of the 12 Platform-Level Interrupt Controller (PLIC) high-level specification in 13 the RISC-V Privileged Architecture specification. The PLIC connects all 18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 21 Each interrupt can be enabled on per-context basis. Any context can claim [all …]
/freebsd/sys/contrib/device-tree/Bindings/perf/
H A D	riscv,pmu.yaml	`1 # SPDX-License-Identifier: BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/perf/riscv,pmu.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: RISC- [all...]`
/freebsd/sys/riscv/include/
H A D	cpu.h	1 /- 2 Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com> 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 44 #define TRAPF_PC(tfp) ((tfp)->tf_sepc) 45 #define TRAPF_USERMODE(tfp) (((tfp)->tf_sstatus & SSTATUS_SPP) == 0) 47 #define cpu_getstack(td) ((td)->td_frame->tf_sp) 48 #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 60 * Micro-architecture ID register, marchid. 62 * IDs for open-source implementations are allocated globally. Commercial IDs 63 * will have the most-significant bit set. [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVISelDAGToDAG.cpp	1 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISC-V -----===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file defines an instruction selector for the RISC-V target. 11 //===----------------------------------------------------------------------===// 28 #define DEBUG_TYPE "riscv-isel" 29 #define PASS_NAME "RISC-V DAG->DAG Pattern Instruction Selection" 32 "riscv-use-rematerializable-movimm", cl::Hidden, 37 namespace llvm::RISCV { namespace 47 } // namespace llvm::RISCV [all …]
H A D	RISCVISelLowering.cpp	`1 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation ------ [all...]`
H A D	RISCVInstrInfoZfh.td	1 //===-- RISCVInstrInfoZfh.td - RISC-V 'Zfh' instructions ---- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file describes the RISC-V instructions from the standard 'Zfh' 10 // half-precision floating-point extension, version 1.0. 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 15 // RISC-V specific DAG Nodes. 16 //===----------------------------------------------------------------------===// 30 //===----------------------------------------------------------------------===// [all …]
H A D	RISCVInstrInfoD.td	1 //===-- RISCVInstrInfoD.td - RISC-V 'D' instructions -------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file describes the RISC-V instructions from the standard 'D', 10 // Double-Precision Floating-Point instruction set extension. 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 15 // RISC-V specific DAG Nodes. 16 //===----------------------------------------------------------------------===// 30 //===----------------------------------------------------------------------===// [all …]
H A D	RISCVInstrInfoF.td	1 //===-- RISCVInstrInfoF.td - RISC-V 'F' instructions -------- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file describes the RISC-V instructions from the standard 'F', 10 // Single-Precision Floating-Point instruction set extension. 12 //===----------------------------------------------------------------------===// 14 //===----------------------------------------------------------------------===// 15 // RISC-V specific DAG Nodes. 16 //===----------------------------------------------------------------------===// 73 return N->getFlags().hasNoSignedZeros(); [all …]
H A D	RISCVInstrFormats.td	1 //===-- RISCVInstrFormats.td - RISC-V Instruction Formats --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 //===----------------------------------------------------------------------===// 12 // description in the RISC-V User-Level ISA specification as closely as 18 // specification describes immediate encoding in terms of bit-slicing 22 // a 21-bit value (where the LSB is always zero), we describe it as an imm20 25 //===----------------------------------------------------------------------===// 29 // definitions must be kept in-sync with RISCVBaseInfo.h. 74 // with the source vector register groups besides the highest-numbered part of [all …]
H A D	RISCVInstrInfo.td	1 //===-- RISCVInstrInfo.td - Target Description for RISC-V --- tablegen --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file describes the RISC-V instructions in TableGen format. 11 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 14 // RISC-V specific DAG Nodes. 15 //===----------------------------------------------------------------------===// 17 // Target-independent type requirements, but with target-specific formats. 23 // Target-dependent type requirements. [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A D	RISCVInstructionSelector.cpp	1 //===-- RISCVInstructionSelector.cpp ------------------------------ C++ --==// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// RISC-V. 12 //===----------------------------------------------------------------------===// 28 #define DEBUG_TYPE "riscv-isel" 55 // tblgen-erated 'select' implementation, used as the initial selector for 124 // FIXME: This is necessary because DAGISel uses "Subtarget->" and GlobalISel 165 MachineRegisterInfo &MRI = MF->getRegInfo(); in selectShiftMask() 181 // instructions as well as 32-bit ones): in selectShiftMask() [all …]
/freebsd/share/man/man7/
H A D	arch.7	1 .\" Copyright (c) 2016-2017 The FreeBSD Foundation. 32 .Nd Architecture-specific details 40 For full details consult the processor-specific ABI supplement 97 .Bl -column -offset indent "Architecture" "Initial Release" 110 .Bl -column -offset indent "Architecture" "Initial Release" "Final Release" 141 .Bl -tag -width "Dv L64PC128" 148 types machine representations all have 4-byte size. 172 Typically these are 64-bit machines, where the 178 environment, which was the historical 32-bit predecessor for 64-bit evolution. 180 .Bl -column -offset indent "powerpc64" "ILP32 counterpart" [all …]
/freebsd/contrib/llvm-project/llvm/lib/TargetParser/
H A D	RISCVISAInfo.cpp	1 //===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ----------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 84 outs() << "All available -march extensions for RISC-V\n\n"; in printSupportedExtensions() 103 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printSupportedExtensions() 114 outs() << "\nUse -march to specify the target's extension.\n" in printSupportedExtensions() 115 "For example, clang -march=rv32i_v1p0\n"; in printSupportedExtensions() 121 outs() << "Extensions enabled for the given RISC-V target\n\n"; in printEnabledExtensions() 141 if (EnabledFeatureNames.count("experimental-" + Name.str()) != 0) { in printEnabledExtensions() 149 PrintExtension(E.first, Version, DescMap["experimental-" + E.first]); in printEnabledExtensions() [all …]
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A D	LoongArch.cpp	1 //===- LoongArch.cpp ------------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 75 // produces a PC-relative intermediate value with the lowest 12 bits zeroed (the 80 // Here a "page" is in fact just another way to refer to the 12-bit range 95 // (lu32i.d and lu52i.d). Compensate all the sign-extensions is a bit in getLoongArchPageDelta() 103 pcalau12i_pc = pc - 8; in getLoongArchPageDelta() 109 pcalau12i_pc = pc - 12; in getLoongArchPageDelta() 115 uint64_t result = getLoongArchPage(dest) - getLoongArchPage(pcalau12i_pc); in getLoongArchPageDelta() 117 result += 0x1000 - 0x1'0000'0000; in getLoongArchPageDelta() [all …]
/freebsd/contrib/llvm-project/clang/lib/Sema/
H A D	SemaDeclAttr.cpp	1 //===--- SemaDeclAttr.cpp - Declaration Attribute Handling ----------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 9 // This file implements decl-related attribute processing. 11 //===----------------------------------------------------------------------===// 105 S.Diag(Expr->getExprLoc(), diag::err_ice_too_large) in checkPositiveIntArgument() 117 const auto Literal = dyn_cast<StringLiteral>(E->IgnoreParenCasts()); in checkStringLiteralArgumentAttr() 119 ArgLocation = E->getBeginLoc(); in checkStringLiteralArgumentAttr() 121 if (!Literal \|\| (!Literal->isUnevaluated() && !Literal->isOrdinary())) { in checkStringLiteralArgumentAttr() 122 Diag(E->getBeginLoc(), diag::err_attribute_argument_type) in checkStringLiteralArgumentAttr() [all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A D	DAGCombiner.cpp	1 //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 16 //===----------------------------------------------------------------------===// 88 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 89 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 99 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 103 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true), 108 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden, 109 cl::desc("Only use DAG-combiner alias analysis in this" [all …]
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A D	AttrDocs.td	1 //==--- AttrDocs.td - Attribute documentation ----------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===---------------------------------------------------------------------===// 9 // To test that the documentation builds cleanly, you must run clang-tblgen to 15 // To run clang-tblgen to generate the .rst file: 16 // clang-tblgen -gen-attr-docs -I <root>/llvm/tools/clang/include 17 // <root>/llvm/tools/clang/include/clang/Basic/Attr.td -o 20 // To run sphinx to generate the .html files (note that sphinx-build must be 24 // Non-Windows (from within the clang\docs directory): 25 // sphinx-build -b html _build/html [all …]
/freebsd/contrib/llvm-project/clang/include/clang/Driver/
H A D	Options.td	1 //===--- Options.td - Options for clang -----------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 38 // The option is a "driver"-only option, and should not be forwarded to other 39 // tools via `-Xarch` options. 42 // LinkerInput - The option is a linker input. 45 // NoArgumentUnused - Don't report argument unused warnings for this option; this 46 // is useful for options like -static or -dynamic which a user may always end up 50 // Unsupported - The option is unsupported, and the driver will reject command [all …]