| /linux/Documentation/input/ |
| H A D | gamepad.rst | 1 ---------------------------
3 ---------------------------
11 having user-space deal with different button-mappings for each gamepad, this
25 | <===DP===> |SE| |ST| (W) -|- (E) | |
35 D-Pad Left Right Action Pad
43 - Action-Pad
44 4 buttons in diamonds-shape (on the right side). The buttons are
47 - D-Pad (Direction-pad)
48 4 buttons (on the left side) that point up, down, left and right.
49 - Menu-Pad
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| /linux/drivers/media/platform/verisilicon/ |
| H A D | rockchip_vpu2_hw_jpeg_enc.c | 1 // SPDX-License-Identifier: GPL-2.0
8 * ------------
10 * The quantization coefficients are 8-bit values, complying with
20 * VEPU_swreg_0-VEPU_swreg_15, and chroma table values to
21 * VEPU_swreg_16-VEPU_swreg_31. A special order is needed, neither
26 #include <media/v4l2-mem2mem.h>
42 * The format width and height are already macroblock aligned in rockchip_vpu2_set_src_img_ctrl()
45 * .vidioc_s_selection(), and the width is 4-aligned. in rockchip_vpu2_set_src_img_ctrl()
47 overfill_r = ctx->src_fmt.width - ctx->dst_fmt.width; in rockchip_vpu2_set_src_img_ctrl()
48 overfill_b = ctx->src_fmt.height - ctx->dst_fmt.height; in rockchip_vpu2_set_src_img_ctrl()
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| /linux/drivers/video/fbdev/kyro/ |
| H A D | STG4000OverlayDevice.c | 57 /*clipped on-screen pixel position of overlay */
63 /*clipped pixel pos of source data within buffer thses need to be 128 bit word aligned */
69 /* on-screen pixel position of overlay */
152 return -EINVAL; in CreateOverlaySurface()
155 /* Stride in 16 byte words - 16Bpp */ in CreateOverlaySurface()
226 * Make sure that LUT not used - ?????? in CreateOverlaySurface()
280 return -EINVAL; in SetOverlayBlendMode()
309 ulBits--; in Overlap()
319 u32 right, u32 bottom) in SetOverlayViewPort() argument
348 srcDest.ulSrcX2 = ovlWidth - 1; in SetOverlayViewPort()
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/ |
| H A D | spec_operation.json | 8 "PublicDescription": "Counts branches speculatively executed and were predicted right."
16 …he actual instruction), even if they are subsequently issued as multiple aligned accesses. The eve…
20 …ned by the actual instruction), even if they are subsequently issued as multiple aligned accesses."
24 …ned by the actual instruction), even if they are subsequently issued as multiple aligned accesses."
28 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: …
32 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and …
36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and …
40 … "PublicDescription": "Counts store-exclusive operations that have been speculatively executed."
56 …ively executed Advanced SIMD operations excluding load, store and move micro-operations that move …
80 …udes operations that force a software change of the PC, other than exception-generating operations…
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| /linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-v1/ |
| H A D | spec_operation.json | 8 "PublicDescription": "Counts branches speculatively executed and were predicted right."
16 …"PublicDescription": "Counts micro-operations speculatively executed. This is the count of the num…
20 …he actual instruction), even if they are subsequently issued as multiple aligned accesses. The eve…
24 …ned by the actual instruction), even if they are subsequently issued as multiple aligned accesses."
28 …ned by the actual instruction), even if they are subsequently issued as multiple aligned accesses."
32 …"PublicDescription": "Counts Load-Exclusive operations that have been speculatively executed. Eg: …
36 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and …
40 …"PublicDescription": "Counts store-exclusive operations that have been speculatively executed and …
44 … "PublicDescription": "Counts store-exclusive operations that have been speculatively executed."
60 …ively executed Advanced SIMD operations excluding load, store and move micro-operations that move …
[all …]
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| /linux/arch/mips/include/asm/ |
| H A D | maar.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
14 * platform_maar_init() - perform platform-level MAAR configuration
18 * MAAR pairs as required, from 0 up to the maximum of num_pairs-1, and returns
28 * write_maar_pair() - write to a pair of MAARs
31 * aligned to a 2^16 byte boundary.
33 * aligned to one byte before a 2^16 byte boundary.
43 /* Addresses begin at bit 16, but are shifted right 4 bits */ in write_maar_pair()
78 * maar_init() - initialise MAARs
87 * struct maar_config - MAAR configuration data
89 * aligned to a 2^16 byte boundary.
[all …]
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| /linux/drivers/mtd/devices/ |
| H A D | ms02-nv.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * DEC MS02-NV (54-20948-01) battery backed-up NVRAM module for
16 * 0x000000 - 0x3fffff SRAM
17 * 0x400000 - 0x7fffff CSR
22 * 0x000000 - 0x0003ff diagnostic area, destroyed upon a reboot
23 * 0x000400 - ENDofRAM storage area, available to operating systems
25 * but we can't really use the available area right from 0x000400 as
31 * for the start address of the user-available is 0x001000 which is
32 * nicely page aligned. The area between 0x000404 and 0x000fff may
36 * operating system, a magic ID to distinguish a MS02-NV board from
[all …]
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| /linux/arch/mips/kernel/ |
| H A D | jump_label.c | 23 * - the ISA bit of the target, either 0 or 1 respectively,
25 * - the amount the jump target address is shifted right to fit in the
28 * - the mask determining the size of the jump region relative to the
29 * delay-slot instruction, either 256MB or 128MB,
31 * - the jump target alignment, either 4 or 2 bytes.
34 #define J_RANGE_SHIFT (2 - J_ISA_BIT)
35 #define J_RANGE_MASK ((1ul << (26 + J_RANGE_SHIFT)) - 1)
36 #define J_ALIGN_MASK ((1ul << J_RANGE_SHIFT) - 1)
45 insn_p = (union mips_instruction *)msk_isa16_mode(e->code); in arch_jump_label_transform()
47 /* Target must have the right alignment and ISA must be preserved. */ in arch_jump_label_transform()
[all …]
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| /linux/tools/testing/selftests/powerpc/alignment/ |
| H A D | copy_first_unaligned.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Calls to copy_first which are not 128-byte aligned should be
22 unsigned int *pc = (unsigned int *)ctx->uc_mcontext.gp_regs[PT_NIP]; in signal_action_handler()
24 unsigned int *pc = (unsigned int *)ctx->uc_mcontext.uc_regs->gregs[PT_NIP]; in signal_action_handler()
32 _exit(0); /* We hit the right instruction */ in signal_action_handler()
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| /linux/fs/cramfs/ |
| H A D | README | 2 --------------------------
9 All data is currently in host-endian format; neither mkcramfs nor the
22 Filename. Not generally null-terminated, but it is
23 null-padded to a multiple of 4 bytes.
25 The order of inode traversal is described as "width-first" (not to be
26 confused with breadth-first); i.e. like depth-first but listing all of
28 same order as `ls -AUR' (but without the /^\..*:$/ directory header
29 lines); put another way, the same order as `find -type d -exec
30 ls -AU1 {} \;'.
34 exist, speeds up user-space directory sorts, etc.
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| /linux/rust/kernel/ |
| H A D | workqueue.rs | 1 // SPDX-License-Identifier: GPL-2.0
11 //! generic, they are used only at compile-time, so they shouldn't exist in the final binary.
51 //! fn new(value: i32) -> Result<Arc<Self>> {
54 //! work <- new_work!("MyStruct::work"),
97 //! fn new(value_1: i32, value_2: i32) -> Result<Arc<Self>> {
101 //! work_1 <- new_work!("MyStruct::work_1"),
102 //! work_2 <- new_work!("MyStruct::work_2"),
152 //! fn new(value: i32) -> Resul
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| /linux/Documentation/translations/ |
| H A D | index.rst | 21 ----------
34 immediately to all translations. Translations' maintainers - and
35 contributors - follow the evolution of the official documentation and they
36 maintain translations aligned as much as they can. For this reason there is
38 translation does not sound right compared to what you read in the code, please
39 inform the translation maintainer and - if you can - check also the English
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | msr.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
24 4-byte alignment physical address of a memory area which must be
42 An odd version indicates an in-progress update.
53 Note that although MSRs are per-CPU entities, the effect of this
63 4-byte aligned physical address of a memory area which must be in
80 updates of this structure is arbitrary and implementation-dependent.
89 An odd version indicates an in-progress update.
104 tsc-related quantity to nanoseconds
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| /linux/drivers/fsi/ |
| H A D | cf-fsi-fw.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
61 * +---------------------------+
64 * +---------------------------+
110 * Last byte of message must be left aligned
114 /* Response data area, right aligned, unused top bits are 1 */
118 #define INT_CNT 0x30 /* 32-bit interrupt count */
119 #define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */
120 #define CF_STARTED 0x38 /* byte, set to -1 when copro started */
121 #define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */
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| /linux/drivers/block/drbd/ |
| H A D | drbd_interval.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * interval_end - return end of @node
13 return this->end; in interval_end()
16 #define NODE_END(node) ((node)->sector + ((node)->size >> 9))
22 * drbd_insert_interval - insert a new interval into a tree
27 struct rb_node **new = &root->rb_node, *parent = NULL; in drbd_insert_interval()
28 sector_t this_end = this->sector + (this->size >> 9); in drbd_insert_interval()
30 BUG_ON(!IS_ALIGNED(this->size, 512)); in drbd_insert_interval()
37 if (here->end < this_end) in drbd_insert_interval()
38 here->end = this_end; in drbd_insert_interval()
[all …]
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| /linux/arch/alpha/lib/ |
| H A D | ev6-clear_user.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-clear_user.S
4 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
8 * We have to make sure that $0 is always up-to-date and contains the
9 * right "bytes left to zero" value (and that it is updated only _after_
16 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
18 * E - either cluster
19 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
20 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
25 * it's going to be worth the effort to hand-unroll a big loop, and use wh64.
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| /linux/tools/testing/selftests/powerpc/stringloops/ |
| H A D | memcmp_64.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/ppc-opcode.h>
42 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
43 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
44 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
46 stdu r1,-STACKFRAMESIZE(r1); \
58 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
59 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
60 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
62 stdu r1,-STACKFRAMESIZE(r1); \
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| /linux/arch/powerpc/lib/ |
| H A D | memcmp_64.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 #include <asm/ppc-opcode.h>
42 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
43 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
44 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
46 stdu r1,-STACKFRAMESIZE(r1); \
58 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
59 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
60 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
62 stdu r1,-STACKFRAMESIZE(r1); \
[all …]
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| /linux/arch/arm/mm/ |
| H A D | cache-uniphier.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015-2016 Socionext Inc.
15 #include <asm/hardware/cache-uniphier.h>
21 #define UNIPHIER_SSCC_ACT BIT(19) /* Inst-Data separate */
23 #define UNIPHIER_SSCC_PRD BIT(17) /* enable pre-fetch */
37 #define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
61 * struct uniphier_cache_data - UniPhier outer cache specific data
93 * __uniphier_cache_sync - perform a sync point for a particular cache level
101 data->op_base + UNIPHIER_SSCOPE); in __uniphier_cache_sync()
103 readl_relaxed(data->op_base + UNIPHIER_SSCOPE); in __uniphier_cache_sync()
[all …]
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| /linux/Documentation/fb/ |
| H A D | pxafb.rst | 10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
37 right:RIGHT == LCCR1_ELW + 1
87 PXA27x and later processors support overlay1 and overlay2 on-top of the
88 base framebuffer (although under-neath the base is also possible). They
89 support palette and no-palette RGB formats, as well as YUV formats (only
96 1. overlay can start at a 32-bit word aligned position within the base
98 is encoded into var->nonstd (no, var->xoffset and var->yoffset are
104 var->xres_virtual * var->yres_virtual * bpp
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| /linux/mm/ |
| H A D | fadvise.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/backing-dev.h>
42 if (S_ISFIFO(inode->i_mode)) in generic_fadvise()
43 return -ESPIPE; in generic_fadvise()
45 mapping = file->f_mapping; in generic_fadvise()
47 return -EINVAL; in generic_fadvise()
49 bdi = inode_to_bdi(mapping->host); in generic_fadvise()
62 return -EINVAL; in generic_fadvise()
76 endbyte--; /* inclusive */ in generic_fadvise()
80 file->f_ra.ra_pages = bdi->ra_pages; in generic_fadvise()
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| H A D | percpu-internal.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
30 the right side of the block */
75 region to have a page aligned
79 aligned */
111 * pcpu_chunk_nr_blocks - converts nr_pages to # of md_blocks
119 return chunk->nr_pages * PAGE_SIZE / PCPU_BITMAP_BLOCK_SIZE; in pcpu_chunk_nr_blocks()
123 * pcpu_nr_pages_to_map_bits - converts the pages to size of bitmap
135 * pcpu_chunk_map_bits - helper to convert nr_pages to size of bitmap
143 return pcpu_nr_pages_to_map_bits(chunk->nr_pages); in pcpu_chunk_map_bits()
147 * pcpu_obj_full_size - helper to calculate size of each accounted object
[all …]
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| /linux/Documentation/process/ |
| H A D | code-of-conduct.rst | 11 our community a harassment-free experience for everyone, regardless of age, body
13 expression, level of experience, education, socio-economic status, nationality,
48 Maintainers have the right and responsibility to remove, edit, or reject
50 not aligned to this Code of Conduct, or to ban temporarily or permanently any
59 representing a project or community include using an official project e-mail
80 available at https://www.contributor-covenant.org/version/1/4/code-of-conduct.html
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| /linux/arch/arm/kernel/ |
| H A D | head-common.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-common.S
5 * Copyright (C) 1994-2002 Russell King
18 #define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
24 * we're even running on the right architecture, we do virtually nothing.
33 * that the pointer be aligned, in the first 16k of physical RAM and
44 tst r2, #0x3 @ aligned?
71 * r0 = cp#15 control register (exc_ret for M-class)
149 .size __mmap_switched_data, . - __mmap_switched_data
155 * This provides a C-API version of __lookup_processor_type
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| /linux/include/uapi/drm/ |
| H A D | qxl_drm.h | 34 * subject to backwards-compatibility constraints.
37 * compatibility Keep fields aligned to their size
102 __u32 right; member
106 #define QXL_PARAM_NUM_SURFACES 1 /* rom->n_surfaces */
|