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Searched +full:rf +full:- +full:filt +full:- +full:enable (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/net/ieee802154/
H A Dmrf24j40.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
92 #define REG_RFCTL 0x36 /* RF Control Mode Register */
110 #define REG_RFCON0 0x200 /* RF Control Registers */
150 #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */
151 #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */
184 /* Device configuration: Only channels 11-26 on page 0 are supported. */
188 - ((u32)1 << MRF24J40_CHAN_MIN))
256 #define printdev(X) (&X->spi->dev)
512 return -EINVAL; in mrf24j40_long_regmap_write()
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/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_lp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* Definitions for the LP-PHY */
23 #define B43_LPPHY_RF_SYNTH_DC_TIMER B43_PHY_CCK(0x11) /* RF Synth DC Timer */
166 #define B43_LPPHY_RF_OVERRIDE_0 B43_PHY_OFDM(0x4C) /* RF Override 0 */
167 #define B43_LPPHY_RF_OVERRIDE_VAL_0 B43_PHY_OFDM(0x4D) /* RF Override Val 0 */
178 #define B43_LPPHY_PHY_CRS_ENABLE_ADDR B43_PHY_OFDM(0x58) /* phy CRS Enable Address */
186 #define B43_LPPHY_REG_CRS_ENABLE B43_PHY_OFDM(0x60) /* reg crs enable */
216 #define B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR B43_PHY_OFDM(0x81) /* IQ Enable Wait Time Address */
262 #define B43_LPPHY_LP_RF_SIGNAL_LUT B43_PHY_OFDM(0xAC) /* LP RF signal LUT */
266 #define B43_LPPHY_RF_OVERRIDE_2 B43_PHY_OFDM(0xB0) /* RF override 2 */
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H A Dphy_n.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 Copyright (c) 2010-2011 Rafał Miłecki <zajec5@gmail.com>
96 enum nl80211_band band = b43_current_band(dev->wl); in b43_nphy_ipa()
97 return ((dev->phy.n->ipa2g_on && band == NL80211_BAND_2GHZ) || in b43_nphy_ipa()
98 (dev->phy.n->ipa5g_on && band == NL80211_BAND_5GHZ)); in b43_nphy_ipa()
101 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */
109 * RF (just without b43_nphy_rf_ctl_intc_override)
112 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
137 b43err(dev->wl, "RF sequence status timeout\n"); in b43_nphy_force_rf_sequence()
149 /* https://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */
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/linux/sound/soc/codecs/
H A Dcs42l42.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs42l42.c -- CS42L42 ALSA SoC audio driver
29 #include <sound/soc-dapm.h>
32 #include <dt-bindings/sound/cs42l42.h>
400 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
401 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
410 switch (ucontrol->value.integer.value[0]) { in cs42l42_slow_start_put()
418 return -EINVAL; in cs42l42_slow_start_put()
452 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
479 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in cs42l42_hp_adc_ev()
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