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/linux/Documentation/devicetree/bindings/net/
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
27 "#size-cells":
[all …]
H A Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
[all …]
H A Dhisilicon-hix5hd2-gmac.txt4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
[all …]
H A Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
14 of common properties between various SOC designs. It thus enables us to use
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280-crd-r3.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include "sc7280-idp.dtsi"
11 #include "sc7280-idp-ec-h1.dtsi"
14 model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)";
15 compatible = "qcom,sc7280-crd",
16 "google,hoglin-rev3", "google,hoglin-rev4",
17 "google,piglin-rev3", "google,piglin-rev4",
25 stdout-path = "serial0:115200n8";
30 regulators-2 {
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-acelink-ew-7886cax.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
11 compatible = "acelink,ew-7886cax", "mediatek,mt7986a";
12 model = "Acelink EW-7886CAX";
19 stdout-path = "serial0:115200n8";
28 compatible = "gpio-keys";
30 key-restart {
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-var-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 model = "Variscite VAR-SOM-MX93 module";
13 compatible = "variscite,var-som-mx93", "fsl,imx93";
15 mmc_pwrseq: mmc-pwrseq {
16 compatible = "mmc-pwrseq-simple";
17 post-power-on-delay-ms = <100>;
18 power-off-delay-us = <10000>;
19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
23 reg_eqos_phy: regulator-eqos-phy {
[all …]
/linux/drivers/net/ethernet/emulex/benet/
H A Dbe_hw.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
16 * The software must write this register twice to post any command. First,
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
39 /* Soft Reset register masks */
42 /* MPU semphore POST stage values */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
45 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
46 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779g2-white-hawk-single.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board
8 /dts-v1/;
10 #include "white-hawk-cpu-common.dtsi"
11 #include "white-hawk-common.dtsi"
15 compatible = "renesas,white-hawk-single", "renesas,r8a779g2",
20 uart-has-rtscts;
38 bias-disable;
43 drive-strength = <24>;
44 bias-disable;
[all …]
/linux/arch/riscv/boot/dts/thead/
H A Dth1520-beaglev-ahead.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
15 compatible = "beagle,beaglev-ahead", "thead,th1520";
35 stdout-path = "serial0:115200n8";
44 pinctrl-names = "default";
45 pinctrl-0 = <&led_pins>;
46 compatible = "gpio-leds";
48 led-1 {
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-dhcor-testbench.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
17 stdout-path = "serial0:115200n8";
20 sd_switch: regulator-sd_switch {
21 compatible = "regulator-gpio";
22 regulator-name = "sd_switch";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <2900000>;
25 regulator-type = "voltage";
26 regulator-always-on;
29 gpios-states = <0>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-apf6.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 reg_1p8v: regulator-1p8v {
10 compatible = "regulator-fixed";
11 regulator-name = "1P8V";
12 regulator-min-microvolt = <1800000>;
13 regulator-max-microvolt = <1800000>;
14 regulator-always-on;
15 vin-supply = <&reg_3p3v>;
[all …]
H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 power-supply = <&reg_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
33 gpio_buttons: gpio-keys {
[all …]
H A Dimx7d-flex-concentrator.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "imx7d-tqma7.dtsi"
14 /delete-node/ &ds1339;
18 compatible = "kam,imx7d-flex-concentrator", "fsl,imx7d";
22 /* 1024 MB - TQMa7D board configuration */
26 reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
27 compatible = "regulator-fixed";
28 regulator-name = "VBUS_USBOTG2";
29 regulator-min-microvolt = <5000000>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3566-radxa-zero-3w.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include "rk3566-radxa-zero-3.dtsi"
9 compatible = "radxa,zero-3w", "rockchip,rk3566";
17 sdio_pwrseq: sdio-pwrseq {
18 compatible = "mmc-pwrseq-simple";
20 clock-names = "ext_clock";
21 pinctrl-names = "default";
22 pinctrl-0 = <&wifi_reg_on_h>;
23 post-power-on-delay-ms = <100>;
[all …]
/linux/drivers/w1/
H A Dw1_io.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/delay.h>
48 * w1_touch_bit() - Generates a write-0 or write-1 cycle and samples the level.
50 * @bit: 0 - write a 0, 1 - write a 0 read the level
54 if (dev->bus_master->touch_bit) in w1_touch_bit()
55 return dev->bus_master->touch_bit(dev->bus_master->data, bit); in w1_touch_bit()
66 * w1_write_bit() - Generates a write-0 or write-1 cycle.
70 * Only call if dev->bus_master->touch_bit is NULL
79 dev->bus_master->write_bit(dev->bus_master->data, 0); in w1_write_bit()
81 dev->bus_master->write_bit(dev->bus_master->data, 1); in w1_write_bit()
[all …]
/linux/arch/arm/boot/dts/actions/
H A Dowl-s500-roseapplepi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (C) 2020-2021 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
8 /dts-v1/;
10 #include "owl-s500.dtsi"
22 stdout-path = "serial2:115200n8";
30 syspwr: regulator-5v0 {
31 compatible = "regulator-fixed";
32 regulator-name = "SYSPWR";
33 regulator-min-microvolt = <5000000>;
34 regulator-max-microvolt = <5000000>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-evm-quad-port-eth-exp.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
14 #include "k3-pinctrl.h"
15 #include "k3-serdes.h"
19 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
20 ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
21 ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
[all …]
H A Dk3-j721e-evm-quad-port-eth-exp.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
6 * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/phy/phy-cadence.h>
16 #include "k3-pinctrl.h"
17 #include "k3-serdes.h"
21 ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h5-nanopi-neo-plus2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 /dts-v1/;
6 #include "sun50i-h5.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/pinctrl/sun4i-a10.h>
14 compatible = "friendlyarm,nanopi-neo-plus2", "allwinner,sun50i-h5";
22 stdout-path = "serial0:115200n8";
26 compatible = "gpio-leds";
28 led-0 {
[all …]
/linux/arch/arm/mach-omap2/
H A Dsram242x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram242x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
69 /* reset entry mode for dllctrl */
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
H A Dsram243x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/arch/arm/mach-omap2/sram243x.S
9 * Richard Woodruff <r-woodruff2@ti.com>
31 stmfd sp!, {r0 - r12, lr} @ save registers on stack
39 str r3, [r2] @ go to L1-freq operation
62 mov r9, #0x0 @ shift back to L0-voltage
67 str r3, [r2] @ go to L0-freq operation
69 /* reset entry mode for dllctrl */
82 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
[all …]
/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-s3-pinecube.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
6 /dts-v1/;
7 #include "sun8i-v3.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
13 compatible = "pine64,pinecube", "sochip,s3", "allwinner,sun8i-v3";
20 stdout-path = "serial0:115200n8";
24 compatible = "gpio-leds";
38 compatible = "regulator-fixed";
39 regulator-name = "vcc5v0";
[all …]

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