| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
27 "#size-cells":
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| H A D | fsl-fec.txt | 4 - compatible : Should be "fsl,<soc>-fec"
5 - reg : Address and length of the register set for the device
6 - interrupts : Should contain fec interrupt
7 - phy-mode : See ethernet.txt file in the same directory
10 - phy-supply : regulator that powers the Ethernet PHY.
11 - phy-handle : phandle to the PHY device connected to this device.
12 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
13 Use instead of phy-handle.
14 - fsl,num-tx-queues : The property is valid for enet-avb IP, which supports
17 - fsl,num-rx-queues : The property is valid for enet-avb IP, which supports
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| H A D | fsl,fec.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
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| H A D | ethernet-phy.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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| H A D | hisilicon-femac.txt | 4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
14 the PHY reset signal(optional).
15 - reset-names: should contain the reset signal name "mac"(required)
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| /freebsd/sys/contrib/device-tree/Bindings/power/reset/ |
| H A D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpi
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| H A D | gpio-restart.txt | 4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
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| /freebsd/sys/contrib/device-tree/Bindings/display/panel/ |
| H A D | samsung,s6e8aa0.txt | 4 - compatible: "samsung,s6e8aa0"
5 - reg: the virtual channel number of a DSI peripheral
6 - vdd3-supply: core voltage supply
7 - vci-supply: voltage supply for analog circuits
8 - reset-gpios: a GPIO spec for the reset pin
9 - display-timings: timings for the connected panel as described by [1]
12 - power-on-delay: delay after turning regulators on [ms]
13 - reset-delay: delay after reset sequence [ms]
14 - init-delay: delay after initialization sequence [ms]
15 - panel-width-mm: physical panel width [mm]
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| H A D | samsung,s6e8aa0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
22 reset-gpios: true
23 display-timings: true
25 vdd3-supply:
28 vci-supply:
31 power-on-delay:
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| H A D | samsung,ld9040.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 display-timings: true
25 reset-gpios: true
27 vdd3-supply:
30 vci-supply:
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| /freebsd/sys/contrib/device-tree/Bindings/c6x/ |
| H A D | clocks.txt | 2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
18 - reg: base address and size of register area
19 - clock-frequency: input clock frequency in hz
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
9 - reg : Contains two entries, each of which is a tuple consisting of a
13 - interrupts : Unit interrupt specifier for the controller interrupt.
14 - clocks : phandle to the Quad SPI clock.
15 - cdns,fifo-depth : Size of the data FIFO in words.
16 - cdns,fifo-width : Bus width of the data FIFO in bytes.
[all …]
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| H A D | nvidia,tegra114-spi.txt | 4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
9 - clock-names : Must include the following entries:
10 - spi
11 - resets : Must contain an entry for each entry in reset-names.
12 See ../reset/reset.txt for details.
13 - reset-names : Must include the following entries:
14 - spi
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | mmc-pwrseq-simple.txt | 8 - compatible : contains "mmc-pwrseq-simple".
11 - reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted
13 They will be de-asserted right after the power has been provided to the
15 - clocks : Must contain an entry for the entry in clock-names.
16 See ../clocks/clock-bindings.txt for details.
17 - clock-names : Must include the following entry:
19 - post-power-on-delay-ms : Delay in ms after powering the card and
20 de-asserting the reset-gpios (if any)
21 - power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
27 compatible = "mmc-pwrseq-simple";
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| H A D | mmc-pwrseq-simple.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
33 description: Handle for the entry in clock-names.
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| H A D | mtk-sd.txt | 10 - compatible: value should be either of the following.
11 "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12 "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
14 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
15 "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
16 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
17 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
18 "mediatek,mt7622-mmc": for MT7622 SoC
19 "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
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| /freebsd/sys/contrib/device-tree/Bindings/input/ |
| H A D | nvidia,tegra20-kbc.txt | 7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
14 - linux,keymap: The keymap for keys as described in the binding document
15 devicetree/bindings/input/matrix-keymap.txt.
16 - clocks: Must contain one entry, for the module clock.
17 See ../clocks/clock-bindings.txt for details.
18 - resets: Must contain an entry for each entry in reset-names.
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra20-usb-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra124-usb-phy
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| /freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
| H A D | vitesse,vsc73xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Vitesse DSA Switches were produced in the early-to-mid 2000s.
19 Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
20 Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
21 Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
22 Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
27 reside inside a SPI bus device tree node, see spi/spi-bus.txt
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| /freebsd/sys/contrib/device-tree/src/arm64/rockchip/ |
| H A D | rk3588-turing-rk1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Based on RK3588-EVB1 devicetree
11 /dts-v1/;
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/pinctrl/rockchip.h>
24 fan: pwm-fan {
25 compatible = "pwm-fan";
26 cooling-levels = <0 25 95 145 195 255>;
27 fan-supply = <&vcc5v0_sys>;
28 pinctrl-names = "default";
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| /freebsd/sys/contrib/device-tree/src/arm/nvidia/ |
| H A D | tegra124.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-binding
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| /freebsd/sys/contrib/device-tree/src/arm64/nvidia/ |
| H A D | tegra132.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | google,cros-ec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Guenter Roeck <groeck@chromium.org>
22 - description:
24 const: google,cros-ec-i2c
25 - description:
27 const: google,cros-ec-spi
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| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | nxp,lpc1850-rgu.txt | 1 NXP LPC1850 Reset Generation Unit (RGU)
4 Please also refer to reset.txt in this directory for common reset
8 - compatible: Should be "nxp,lpc1850-rgu"
9 - reg: register base and length
10 - clocks: phandle and clock specifier to RGU clocks
11 - clock-names: should contain "delay" and "reg"
12 - #reset-cells: should be 1
14 See table below for valid peripheral reset numbers. Numbers not
18 Reset Peripheral
20 12 ARM Cortex-M0 subsystem core (LPC43xx only)
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