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/linux/Documentation/devicetree/bindings/w1/
H A Dw1-uart.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/w1/w1-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART 1-Wire Bus
10 - Christoph Winklhofer <cj.winklhofer@gmail.com>
13 UART 1-wire bus. Utilizes the UART interface via the Serial Device Bus
14 to create the 1-Wire timing patterns.
16 The UART peripheral must support full-duplex and operate in open-drain
18 baud-rate and transmitted byte, which corresponds to a 1-Wire read bit,
[all …]
/linux/arch/m68k/atari/
H A Ddebug.c6 * Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek
23 /* Can be set somewhere, if a SCC master reset has already be done and should
31 .index = -1,
45 while (count--) { in atari_mfp_console_write()
64 while (count--) { in atari_scc_console_write()
81 while (count--) { in atari_midi_console_write()
91 /* This a some-seconds timeout in case no printer is connected */ in ata_par_out()
94 while ((st_mfp.par_dt_reg & 1) && --i) /* wait for BUSY == L */ in ata_par_out()
117 while (count--) { in atari_par_console_write()
164 * timer values for 1200...115200 bps; > 38400 select 110, 134, or 150 in atari_init_mfp_port()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,pef2256.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
20 - const: lantiq,pef2256
27 - description: Master Clock
28 - description: System Clock Receive
29 - description: System Clock Transmit
31 clock-names:
33 - const: mclk
[all …]
/linux/drivers/soundwire/
H A Dgeneric_bandwidth_allocation.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
39 unsigned int rate, bps, ch = 0; in sdw_compute_slave_ports() local
41 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
43 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
45 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
46 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
47 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
48 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
51 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_slave_ports()
[all …]
H A Dstream.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-18 Intel Corporation.
5 * stream.c - SoundWire Bus stream operations.
74 if (bus->params.next_bank) { in _sdw_program_slave_port_params()
75 addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num); in _sdw_program_slave_port_params()
76 addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num); in _sdw_program_slave_port_params()
77 addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num); in _sdw_program_slave_port_params()
78 addr4 = SDW_DPN_HCTRL_B1(t_params->port_num); in _sdw_program_slave_port_params()
80 addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num); in _sdw_program_slave_port_params()
81 addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num); in _sdw_program_slave_port_params()
[all …]
/linux/include/media/i2c/
H A Dtc358743.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tc358743 - Toshiba HDMI to CSI-2 bridge
10 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
11 * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
51 /* Bps pr lane is (refclk_hz / pll_prd) * pll_fbd */
61 * bps pr lane is 823.5 MHz, and can serve as a starting point.
73 /* DVI->HDMI detection delay to avoid unnecessary switching between DVI
80 /* Reset PHY automatically when TMDS clock goes from DC to AC.
86 /* Reset PHY automatically when TMDS clock passes 21 MHz.
92 /* Reset PHY automatically when TMDS clock is detected.
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_virt.c45 vf2pf_info->ucode_info[ucode].id = ucode; \
46 vf2pf_info->ucode_info[ucode].version = ver; \
74 if (adev->asic_type != CHIP_ALDEBARAN && in amdgpu_virt_init_setting()
75 adev->asic_type != CHIP_ARCTURUS && in amdgpu_virt_init_setting()
76 ((adev->pdev->class >> 8) != PCI_CLASS_ACCELERATOR_PROCESSING)) { in amdgpu_virt_init_setting()
77 if (adev->mode_info.num_crtc == 0) in amdgpu_virt_init_setting()
78 adev->mode_info.num_crtc = 1; in amdgpu_virt_init_setting()
79 adev->enable_virtual_display = true; in amdgpu_virt_init_setting()
81 ddev->driver_features &= ~DRIVER_ATOMIC; in amdgpu_virt_init_setting()
82 adev->cg_flags = 0; in amdgpu_virt_init_setting()
[all …]
/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
58 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
60 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
61 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
62 #define ERR_RES 0x30 /* Error Reset */
63 #define RES_H_IUS 0x38 /* Reset highest IUS */
65 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
66 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
67 #define RES_EOM_L 0xC0 /* Reset EOM latch */
[all …]
H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
50 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
52 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
53 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
54 #define ERR_RES 0x30 /* Error Reset */
55 #define RES_H_IUS 0x38 /* Reset highest IUS */
57 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
58 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
59 #define RES_EOM_L 0xC0 /* Reset EOM latch */
[all …]
H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
52 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) argument
78 #define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
80 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
81 #define RES_Tx_P 0x28 /* Reset TxINT Pending */
82 #define ERR_RES 0x30 /* Error Reset */
83 #define RES_H_IUS 0x38 /* Reset highest IUS */
85 #define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
86 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
[all …]
H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
/linux/drivers/net/can/dev/
H A Dcalc_bittiming.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2005 Marc Kleine-Budde, Pengutronix
4 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
5 * Copyright (C) 2021-2025 Vincent Mailhol <mailhol@kernel.org>
16 if (bt->bitrate > 800 * KILO /* BPS */) in can_calc_sample_point_nrz()
19 if (bt->bitrate > 500 * KILO /* BPS */) in can_calc_sample_point_nrz()
25 /* Sample points for Pulse-Width Modulation encoding. */
28 if (bt->bitrate > 15 * MEGA /* BPS */) in can_calc_sample_point_pwm()
31 if (bt->bitrate > 9 * MEGA /* BPS */) in can_calc_sample_point_pwm()
34 if (bt->bitrate > 4 * MEGA /* BPS */) in can_calc_sample_point_pwm()
[all …]
H A Dnetlink.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2005 Marc Kleine-Budde, Pengutronix
4 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
5 * Copyright (C) 2021-2025 Vincent Mailhol <mailhol@kernel.org>
67 /* sample point is in one-tenth of a percent */ in can_validate_bittiming()
68 if (bt->sample_point >= 1000) { in can_validate_bittiming()
70 return -EINVAL; in can_validate_bittiming()
86 return -EOPNOTSUPP; in can_validate_tdc()
90 * must be set and vice-versa in can_validate_tdc()
94 return -EOPNOTSUPP; in can_validate_tdc()
[all …]
/linux/Documentation/netlink/specs/
H A Dnet_shaper.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
3 name: net-shaper
26 Existing shapers can be deleted/reset via the @delete operation.
33 @cap-get operation.
36 -
38 name: max-handle-id
41 -
45 render-max: true
47 - name: unspec
[all …]
/linux/block/
H A Dblk-throttle.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "blk-cgroup-rwstat.h"
15 #include "blk-throttle.h"
49 return pd_to_blkg(&tg->pd); in tg_to_blkg()
53 * sq_to_tg - return the throl_grp the specified service queue belongs to
56 * Return the throtl_grp @sq belongs to. If @sq is the top-level one
61 if (sq && sq->parent_sq) in sq_to_tg()
68 * sq_to_td - return throtl_data the specified service queue belongs to
79 return tg->td; in sq_to_td()
88 if (cgroup_subsys_on_dfl(io_cgrp_subsys) && !blkg->parent) in tg_bps_limit()
[all …]
/linux/sound/hda/core/
H A Ddevice.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * HD-audio codec core device
28 * snd_hdac_device_init - initialize the HD-audio codec base device
48 dev = &codec->dev; in snd_hdac_device_init()
50 dev->parent = bus->dev; in snd_hdac_device_init()
51 dev->bus = &snd_hda_bus_type; in snd_hdac_device_init()
52 dev->release = default_release; in snd_hdac_device_init()
53 dev->groups = hdac_dev_attr_groups; in snd_hdac_device_init()
57 codec->bus = bus; in snd_hdac_device_init()
58 codec->addr = addr; in snd_hdac_device_init()
[all …]
/linux/drivers/net/wireless/morsemicro/mm81x/
H A Dmmrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017-2026 Morse Micro
54 * Initial and reset probability per rate in the table
98 * Y[n] = X[n] * (100 - EWMA) + (Y[n-1] * EWMA)
99 * -------------------------------------
183 #define MMRC_SHORT_RANGE_RSSI_LIMIT -70
186 #define MMRC_MID_RANGE_RSSI_LIMIT -85
196 * This table stores the number of bits per symbols used for MCS0-MCS9 based
214 return i - 1; in nth_bit()
236 return index - 1; in bit_index()
[all …]
/linux/include/linux/soundwire/
H A Dsdw.h1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
16 #include <linux/device-id/sdw.h>
89 * enum sdw_slave_status - Slave status
107 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
108 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
118 * enum sdw_command_response - Command response as defined by SDW spec
206 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
217 * enum sdw_dpn_type - Data port types
232 * enum sdw_clk_stop_mode - Clock Stop modes
[all …]
/linux/sound/soc/atmel/
H A Dmchp-spdiftx.c1 // SPDX-License-Identifier: GPL-2.0
22 * ---- S/PDIF Transmitter Controller Register map ----
39 * ---- Control Register (Write-only) ----
41 #define SPDIFTX_CR_SWRST BIT(0) /* Software Reset */
45 * ---- Mode Register (Read/Write) ----
92 * ---- Interrupt Enable/Disable/Mask/Status Register (Write/Read-only) ----
205 regmap_read(dev->regmap, SPDIFTX_MR, &mr); in mchp_spdiftx_is_running()
211 struct mchp_spdiftx_mixer_control *ctrl = &dev->control; in mchp_spdiftx_channel_status_write()
215 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat) / 4; i++) { in mchp_spdiftx_channel_status_write()
216 val = (ctrl->ch_stat[(i * 4) + 0] << 0) | in mchp_spdiftx_channel_status_write()
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dmvneta_bm.c32 writel(data, priv->reg_base + offset); in mvneta_bm_write()
37 return readl(priv->reg_base + offset); in mvneta_bm_read()
96 (struct mvneta_bm_pool *)hwbm_pool->priv; in mvneta_bm_construct()
97 struct mvneta_bm *priv = bm_pool->priv; in mvneta_bm_construct()
105 phys_addr = dma_map_single(&priv->pdev->dev, buf, bm_pool->buf_size, in mvneta_bm_construct()
107 if (unlikely(dma_mapping_error(&priv->pdev->dev, phys_addr))) in mvneta_bm_construct()
108 return -ENOMEM; in mvneta_bm_construct()
119 struct platform_device *pdev = priv->pdev; in mvneta_bm_pool_create()
122 size_bytes = sizeof(u32) * bm_pool->hwbm_pool.size; in mvneta_bm_pool_create()
123 bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes, in mvneta_bm_pool_create()
[all …]
/linux/drivers/net/wan/
H A Dfarsync.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards
23 * used with the FarSite T-Series cards (T2P & T4P) running in the high
30 * purpose (FarSite T-series).
75 * FSTCPURESET forces the cards CPU into a reset state and holds it there.
76 * FSTCPURELEASE releases the CPU from this reset state allowing it to run,
77 * the reset vector should be setup before this ioctl is run.
105 unsigned int lineSpeed; /* Speed in bps */
121 unsigned char lineBuildOut; /* 0, -7.5, -15, -22 */
179 #define FST_RESET 1 /* Processor held in reset state */
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-synology-ds116.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include "armada-385.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
14 compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380";
17 stdout-path = "serial0:115200n8";
32 internal-regs {
34 pinctrl-names = "default";
35 pinctrl-0 = <&i2c0_pins>;
37 clock-frequency = <100000>;
[all …]
/linux/drivers/net/wan/framer/pef2256/
H A Dpef2256.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/framer/framer-provider.h>
24 #include "pef2256-regs.h"
59 regmap_read(pef2256->regmap, offset, &val); in pef2256_read8()
65 regmap_write(pef2256->regmap, offset, val); in pef2256_write8()
70 regmap_clear_bits(pef2256->regmap, offset, clr); in pef2256_clrbits8()
75 regmap_set_bits(pef2256->regmap, offset, set); in pef2256_setbits8()
80 regmap_update_bits(pef2256->regmap, offset, clr | set, set); in pef2256_clrsetbits8()
112 dev_err(pef2256->dev, "Unknown version (0x%02x, 0x%02x)\n", vstr, wid); in pef2256_get_version()
123 return sysfs_emit(buf, "%s\n", pef2256->version_txt); in version_show()
[all …]
/linux/drivers/media/platform/renesas/
H A Drenesas-ceu.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c"
9 * Based on V4L2 Driver for PXA camera host - "pxa_camera.c",
16 #include <linux/dma-mapping.h>
32 #include <media/v4l2-async.h>
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-dev.h>
36 #include <media/v4l2-device.h>
[all …]
/linux/sound/soc/codecs/
H A Drt1017-sdca-sdw.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt1017-sdca-sdw.c -- rt1017 SDCA ALSA SoC amplifier audio driver
17 #include <sound/soc-dapm.h>
22 #include "rt1017-sdc
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