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/linux/Documentation/devicetree/bindings/pci/
H A Dintel-gw-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
16 const: intel,lgm-pcie
18 - compatible
21 - $ref: /schemas/pci/snps,dw-pcie.yaml#
26 - const: intel,lgm-pcie
27 - const: snps,dw-pcie
[all …]
/linux/lib/zstd/compress/
H A Dzstd_compress.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
12 /*-*************************************
46 * Maximum size of the hash table dedicated to find 3-bytes matches,
57 /*-*************************************
62 * the one-pass compression functions.
75 /*-*************************************
90 … * row-based matchfinder. Unless the cdict is reloaded, we will use
102 assert(cctx != NULL); in ZSTD_initCCtx()
[all …]
H A Dzstd_lazy.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
24 /*-*************************************
30 void ZSTD_updateDUBT(ZSTD_MatchState_t* ms, in ZSTD_updateDUBT() argument
34 const ZSTD_compressionParameters* const cParams = &ms->cParams; in ZSTD_updateDUBT()
35 U32* const hashTable = ms->hashTable; in ZSTD_updateDUBT()
36 U32 const hashLog = cParams->hashLog; in ZSTD_updateDUBT()
38 U32* const bt = ms->chainTable; in ZSTD_updateDUBT()
39 U32 const btLog = cParams->chainLog - 1; in ZSTD_updateDUBT()
[all …]
H A Dzstd_compress_internal.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
6 * This source code is licensed under both the BSD-style license (found in the
9 * You may select, at your option, one of the above-listed licenses.
19 /*-*************************************
27 /*-*************************************
41 /*-*************************************
86 U16 mlBase; /* mlBase == matchLength - MINMATCH */
127 seqLen.litLength = seq->litLength; in ZSTD_getSequenceLength()
128 seqLen.matchLength = seq->mlBase + MINMATCH; in ZSTD_getSequenceLength()
129 if (seqStore->longLengthPos == (U32)(seq - seqStore->sequencesStart)) { in ZSTD_getSequenceLength()
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
14 - if:
20 - ingenic,jz4770-rtc
21 - ingenic,jz4780-rtc
24 "#clock-cells": false
[all …]
/linux/drivers/scsi/
H A Dmesh.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
12 * Add delay after initial bus reset
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
76 MODULE_PARM_DESC(init_reset_delay, "Initial bus reset delay (0=no reset)");
[all …]
H A Dmesh.h1 /* SPDX-License-Identifier: GPL-2.0 */
64 #define SEQ_ATN 0x20 /* assert ATN signal */
80 #define SEQ_RESETMESH 0x0e /* reset the controller */
114 #define ERR_SCSIRESET 0x20 /* SCSI bus got reset on us */
135 * The units of the sel_timeout register are 10ms.
/linux/Documentation/devicetree/bindings/sound/
H A Dti,tas5086.txt1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
11 chip's !RESET pin. If specified, the driver will
12 assert a hardware reset at probe time.
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
20 When not specified, the hardware default of 1300ms
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/linux/drivers/rtc/
H A Drtc-jz4740.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/clk-provider.h>
75 return readl(rtc->base + reg); in jz4740_rtc_reg_read()
82 return readl_poll_timeout(rtc->base + JZ_REG_RTC_CTRL, ctrl, in jz4740_rtc_wait_write_ready()
95 writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR); in jz4780_rtc_enable_write()
97 return readl_poll_timeout(rtc->base + JZ_REG_RTC_WENR, ctrl, in jz4780_rtc_enable_write()
106 if (rtc->type >= ID_JZ4760) in jz4740_rtc_reg_write()
111 writel(val, rtc->base + reg); in jz4740_rtc_reg_write()
123 spin_lock_irqsave(&rtc->lock, flags); in jz4740_rtc_ctrl_set_bits()
[all …]
/linux/sound/soc/codecs/
H A Dmax98373.c1 // SPDX-License-Identifier: GPL-2.0
23 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98373_dac_event()
28 regmap_update_bits(max98373->regmap, in max98373_dac_event()
34 regmap_update_bits(max98373->regmap, in max98373_dac_event()
38 max98373->tdm_mode = false; in max98373_dac_event()
85 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
101 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
102 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
103 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
104 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-var-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
12 model = "Variscite VAR-SOM-MX93 module";
13 compatible = "variscite,var-som-mx93", "fsl,imx93";
15 mmc_pwrseq: mmc-pwrseq {
16 compatible = "mmc-pwrseq-simple";
17 post-power-on-delay-ms = <100>;
18 power-off-delay-us = <10000>;
19 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
25 pinctrl-names = "default";
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/linux/drivers/pci/controller/dwc/
H A Dpcie-fu740.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2019-2021 SiFive, Inc.
26 #include <linux/reset.h>
28 #include "pcie-designware.h"
30 #define to_fu740_pcie(x) dev_get_drvdata((x)->dev)
35 struct gpio_desc *reset; member
82 /* Assert PERST_N GPIO */ in fu740_pcie_assert_reset()
83 gpiod_set_value_cansleep(afp->reset, 0); in fu740_pcie_assert_reset()
84 /* Assert controller PERST_N */ in fu740_pcie_assert_reset()
85 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N); in fu740_pcie_assert_reset()
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/linux/drivers/macintosh/
H A Dmediabay.c1 // SPDX-License-Identifier: GPL-2.0-or-later
32 #define MB_FCR32(bay, r) ((bay)->base + ((r) >> 2))
33 #define MB_FCR8(bay, r) (((volatile u8 __iomem *)((bay)->base)) + (r))
76 * Wait that number of ms between each step in normal polling mode
81 * Consider the media-bay ID value stable if it is the same for
86 /* Wait after powering up the media bay this delay in ms
92 * Hold the media-bay reset signal true for this many ticks
98 * Wait this long after the reset signal is released and before doing
99 * further operations. After this delay, the IDE reset signal is released
105 * Wait this many ticks after an IDE device (e.g. CD-ROM) is inserted
[all …]
/linux/drivers/phy/ralink/
H A Dphy-ralink-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 #include <linux/reset.h>
63 writel(val, phy->base + reg); in u2_phy_w32()
68 return readl(phy->base + reg); in u2_phy_r32()
97 regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1, in ralink_usb_phy_power_on()
98 phy->clk, phy->clk); in ralink_usb_phy_power_on()
101 regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1, in ralink_usb_phy_power_on()
105 /* deassert the reset lines */ in ralink_usb_phy_power_on()
106 reset_control_deassert(phy->rsthost); in ralink_usb_phy_power_on()
107 reset_control_deassert(phy->rstdev); in ralink_usb_phy_power_on()
[all …]
/linux/drivers/watchdog/
H A Dpnx4008_wdt.c1 // SPDX-License-Identifier: GPL-2.0
12 * 2005-2006 (c) MontaVista Software, Inc.
34 /* WatchDog Timer - Chapter 23 Page 207 */
87 /* stop counter, initiate counter reset */ in pnx4008_wdt_start()
89 /*wait for reset to complete. 100% guarantee event */ in pnx4008_wdt_start()
92 /* internal and external reset, stop after that */ in pnx4008_wdt_start()
98 /* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */ in pnx4008_wdt_start()
100 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start()
121 wdd->timeout = new_timeout; in pnx4008_wdt_set_timeout()
133 * - For details, see the 'reboot' syscall in kernel/reboot.c in pnx4008_restart_handler()
[all …]
/linux/drivers/pps/clients/
H A Dpps-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pps-gpio.c -- PPS client driver using GPIO
9 #define PPS_GPIO_NAME "pps-gpio"
33 struct timer_list echo_timer; /* timer to reset echo active state */
56 rising_edge = info->capture_clear ? in pps_gpio_irq_handler()
57 gpiod_get_value(info->gpio_pin) : !info->assert_falling_edge; in pps_gpio_irq_handler()
58 if ((rising_edge && !info->assert_falling_edge) || in pps_gpio_irq_handler()
59 (!rising_edge && info->assert_falling_edge)) in pps_gpio_irq_handler()
60 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
61 else if (info->capture_clear && in pps_gpio_irq_handler()
[all …]
/linux/include/linux/
H A Drmi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011-2016 Synaptics Incorporated
21 * struct rmi_2d_axis_alignment - target axis alignment
22 * @swap_axes: set to TRUE if desired to swap x- and y-axis
23 * @flip_x: set to TRUE if desired to flip direction on x-axis
24 * @flip_y: set to TRUE if desired to flip direction on y-axis
25 * @clip_x_low - reported X coordinates below this setting will be clipped to
27 * @clip_x_high - reported X coordinates above this setting will be clipped to
29 * @clip_y_low - reported Y coordinates below this setting will be clipped to
31 * @clip_y_high - reported Y coordinates above this setting will be clipped to
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-btt3.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
7 #include "imx28-lwe.dtsi"
12 compatible = "lwn,imx28-btt3", "fsl,imx28";
24 compatible = "powertip,hx8238a", "panel-dpi";
25 power-supply = <&reg_3v3>;
26 width-mm = <70>;
27 height-mm = <52>;
29 panel-timing {
30 clock-frequency = <6500000>;
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-pci-gli.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
21 #include "sdhci-uhs2.h"
374 /* reset the tuning flow after reinit and before starting tuning */ in gli_set_9750()
468 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
481 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
483 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
484 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
[all …]
/linux/drivers/media/i2c/
H A Dadv7183.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
38 * All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
69 return &container_of(ctrl->handler, struct adv7183, hdl)->sd; in to_sd()
95 return -1; in adv7183_writeregs()
185 v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name); in adv7183_log_status()
193 *std = decoder->std; in adv7183_g_std()
220 return -EINVAL; in adv7183_s_std()
223 decoder->std = std; in adv7183_s_std()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dpm3393.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * PMC/SIERRA (pm3393) MAC-PHY functionality. *
14 * Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
87 t1_tpi_read(cmac->adapter, OFFSET(reg), data32); in pmread()
93 t1_tpi_write(cmac->adapter, OFFSET(reg), data32); in pmwrite()
97 /* Port reset. */
115 /* PM3393 - Enabling all hardware block interrupts. in pm3393_interrupt_enable()
138 /* PM3393 - Global interrupt enable in pm3393_interrupt_enable()
144 /* TERMINATOR - PL_INTERRUPTS_EXT */ in pm3393_interrupt_enable()
145 pl_intr = readl(cmac->adapter->regs + A_PL_ENABLE); in pm3393_interrupt_enable()
[all …]
/linux/drivers/scsi/csiostor/
H A Dcsio_mb.c4 * Copyright (c) 2008-2012 Chelsio Communications, Inc. All rights reserved.
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
51 * csio_mb_fw_retval - FW return value from a mailbox response.
60 hdr = (struct fw_cmd_hdr *)(mbp->mb); in csio_mb_fw_retval()
62 return FW_CMD_RETVAL_G(ntohl(hdr->lo)); in csio_mb_fw_retval()
66 * csio_mb_hello - FW HELLO command helper
80 struct fw_hello_cmd *cmdp = (struct fw_hello_cmd *)(mbp->mb); in csio_mb_hello()
84 cmdp->op_to_write = htonl(FW_CMD_OP_V(FW_HELLO_CMD) | in csio_mb_hello()
86 cmdp->retval_len16 = htonl(FW_CMD_LEN16_V(sizeof(*cmdp) / 16)); in csio_mb_hello()
[all …]
/linux/arch/mips/include/asm/sn/
H A Dioc3.h1 /* SPDX-License-Identifier: GPL-2.0 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
153 u32 pad1[(0x20000 - 0x00154) / 4];
157 u32 pad2[(0x40000 - 0x20180) / 4];
160 u32 ssram[(0x80000 - 0x40000) / 4];
163 0x80000 - Access to the generic devices selected with DEV0
165 0xA0000 - Access to the generic devices selected with DEV1
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru-scarlet.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-scarlet board device tree source
8 #include "rk3399-gru.dtsi"
11 chassis-type = "tablet";
16 pp1250_s3: regulator-pp1250-s3 {
17 compatible = "regulator-fixed";
18 regulator-name = "pp1250_s3";
21 regulator-always-on;
22 regulator-boot-on;
23 regulator-min-microvolt = <1250000>;
[all …]
/linux/drivers/pci/controller/
H A Dpcie-mediatek-gen3.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/irqchip/irq-msi-lib.h>
30 #include <linux/reset.h>
79 #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8)
83 GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT)
87 #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
124 (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN)
136 /* Time in ms needed to complete PCIe reset on EN7581 SoC */
152 * struct mtk_gen3_pcie_pdata - differentiate between host generations
[all …]

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