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/linux/Documentation/accounting/
H A Dpsi.rst4 PSI - Pressure Stall Information
14 either play it safe and under-utilize their hardware resources, or
23 scarcity aids users in sizing workloads to hardware--or provisioning
24 hardware according to workload demand.
27 dynamically using techniques such as load shedding, migrating jobs to
29 priority or restartable batch jobs.
31 This allows maximizing hardware utilization without sacrificing
37 Pressure information for each resource is exported through the
38 respective file in /proc/pressure/ -- cpu, memory, and io.
48 The "full" line indicates the share of time in which all non-idle
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/linux/Documentation/admin-guide/cgroup-v1/
H A Dcpusets.rst11 - Portions Copyright (c) 2004-2006 Silicon Graphics, Inc.
12 - Modified by Paul Jackson <pj@sgi.com>
13 - Modified by Christoph Lameter <cl@gentwo.org>
14 - Modified by Paul Menage <menage@google.com>
15 - Modified by Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
41 ----------------------
43 Cpusets provide a mechanism for assigning a set of CPUs and Memory
45 an on-line node that contains memory.
50 hooks, beyond what is already present, required to manage dynamic
54 Documentation/admin-guide/cgroup-v1/cgroups.rst.
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/linux/include/uapi/drm/
H A Dpvr_drm.h1 /* SPDX-License-Identifier: (GPL-2.0-only WITH Linux-syscall-note) OR MIT */
22 * - All members must be type-aligned.
23 * - The overall struct must be padded to 64-bit alignment.
24 * - Explicit padding is almost always required. This takes the form of
25 * ``_padding_[x]`` members of sufficient size to pad to the next power-of-two
27 * are never used for alignment. Padding fields must be zeroed; this is
29 * - Unions may only appear as the last member of a struct.
30 * - Individual union members may grow in the future. The space between the
41 * struct drm_pvr_obj_array - Container used to pass arrays of objects
56 /** @stride: Stride of object struct. Used for versioning. */
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H A Dhabanalabs_accel.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2023 HabanaLabs, Ltd.
14 * Defines that are asic-specific but constitutes as ABI between kernel driver
21 * 128 SOBs reserved for collective wait
22 * 16 SOBs reserved for sync stream
27 * 64 monitors reserved for collective wait
28 * 8 monitors reserved for sync stream
189 * 2. F/W mode, where we use F/W to schedule the JOBS to the different queues.
195 * stream id is a running number from 0 up to (N-1), where N is the number
656 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
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/linux/Documentation/gpu/rfc/
H A Di915_vm_bind.rst11 issued by the UMD, without user having to provide a list of all required
12 mappings during each submission (as required by older execbuf mode).
14 The VM_BIND/UNBIND calls allow UMDs to request a timeline out fence for
18 User has to opt-in for VM_BIND mode of binding for an address space (VM)
31 * Support for userptr gem objects (no special uapi is required for this).
34 ------------------------
35 The i915 driver flushes the TLB for each submission and when an object's
37 TLB flush. Any VM_BIND mapping added will be in the working set for subsequent
38 submissions on that VM and will not be in the working set for currently running
42 -------------------------------
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/linux/Documentation/driver-api/
H A Ddma-buf.rst1 Buffer Sharing and Synchronization (dma-buf)
4 The dma-buf subsystem provides the framework for sharing buffers for
5 hardware (DMA) access across multiple device drivers and subsystems, and
6 for synchronizing asynchronous hardware access.
14 interact with the three main primitives offered by dma-buf:
16 - dma-buf, representing a sg_table and exposed to userspace as a file
19 - dma-fence, providing a mechanism to signal when an asynchronous
20 hardware operation has completed; and
21 - dma-resv, which manages a set of dma-fences for a particular dma-buf
22 allowing implicit (kernel-ordered) synchronization of work to
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/linux/drivers/gpu/drm/v3d/
H A Dv3d_sched.c1 // SPDX-License-Identifier: GPL-2.0+
7 * The shared DRM GPU scheduler is used to coordinate submitting jobs
8 * to the hardware. Each DRM fd (roughly a client process) gets its
9 * own scheduler entity, which will process jobs in order. The GPU
12 * For simplicity, and in order to keep latency low for interactive
13 * jobs when bulk background jobs are queued up, we submit a new job
15 * filling up the CT[01]Q FIFOs with jobs. Similarly, we use
17 * and render, instead of having the clients submit jobs using the HW's
80 if (query_info->queries) { in v3d_timestamp_query_info_free()
83 for (i = 0; i < count; i++) in v3d_timestamp_query_info_free()
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/linux/drivers/media/platform/st/sti/hva/
H A Dhva.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/videobuf2-v4l2.h>
14 #include <media/v4l2-mem2mem.h>
18 #define hva_to_dev(h) (h->dev)
20 #define ctx_to_dev(c) (c->hva_dev->dev)
22 #define ctx_to_hdev(c) (c->hva_dev)
24 #define HVA_NAME "st-hva"
25 #define HVA_PREFIX "[---:----]"
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/linux/Documentation/gpu/
H A Dtegra.rst8 or blocks amongst themselves, can use syncpoints for synchronization.
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
35 tree for matching device nodes, adding the required clients to a list. Drivers
36 for individual clients register with the infrastructure as well and are added
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
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/linux/drivers/dma/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 This is an option for use by developers; most people should
28 This is an option for use by developers; most people should
65 Enable support for Altera / Intel mSGDMA controller.
86 Enable support for the AMCC PPC440SPe RAID engines.
94 Enable support for Audio DMA Controller found on Apple Silicon SoCs.
97 tristate "Arm DMA-350 support"
102 Enable support for the Arm DMA-350 controller.
120 tristate "Analog Devices AXI-DMAC DMA support"
126 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
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H A Dste_dma40.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) Ericsson AB 2007-2008
4 * Copyright (C) ST-Ericsson SA 2008-2010
5 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
9 #include <linux/dma-mapping.h>
32 * struct stedma40_platform_data - Configuration struct for the dma device.
34 * @disabled_channels: A vector, ending with -1, that marks physical channels
35 * that are for different reasons not available for the driver.
38 * SoftLLI introduces relink overhead that could impact performance for
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H A Damba-pl08x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (c) 2010 ST-Ericsson SA
17 * The PL080 has 8 channels available for simultaneous use, and the PL081
27 * - CH_CONFIG register at different offset,
28 * - separate CH_CONTROL2 register for transfer size,
29 * - bigger maximum transfer size,
30 * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
31 * - no support for peripheral flow control.
41 * For peripherals with a FIFO:
45 * (Bursts are irrelevant for mem to mem transfers - there are no burst
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_gem.c17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
30 #include <linux/dma-fence-array.h>
45 mod_timer(&vc4->hangcheck.timer, in vc4_queue_hangcheck()
61 for (i = 0; i < state->user_state.bo_count; i++) in vc4_free_hang_state()
62 drm_gem_object_put(state->bo[i]); in vc4_free_hang_state()
80 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_get_hang_state_ioctl()
81 return -ENODEV; in vc4_get_hang_state_ioctl()
83 if (!vc4->v3d) { in vc4_get_hang_state_ioctl()
85 return -ENODEV; in vc4_get_hang_state_ioctl()
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/linux/include/media/
H A Dv4l2-mem2mem.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Memory-to-memory device framework for Video for Linux 2.
5 * Helper functions for devices that use memory buffers for both source
16 #include <media/videobuf2-v4l2.h>
19 * struct v4l2_m2m_ops - mem-to-mem device driver callbacks
20 * @device_run: required. Begin the actual job (transaction) inside this
30 * that is required for the driver to perform one full transaction.
52 * struct v4l2_m2m_queue_ctx - represents a queue for buffers ready to be
56 * @rdy_queue: List of V4L2 mem-to-mem queues
61 * Queue for buffers ready to be processed as soon as this
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_device.c18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
37 #include <linux/pci-p2pdma.h>
38 #include <linux/apple-gmux.h>
87 #include <asm/intel-family.h>
101 #define AMDGPU_RETRY_SRIOV_RESET(r) ((r) == -EBUSY || (r) == -ETIMEDOUT || (r) == -EINVAL)
152 #define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMD_IP_BLOCK_TYPE_NUM - 1, 0)
170 * is used for cases like reset on initialization where the entire hive needs to
184 return (adev->init_lvl->hwini_ip_block_mask & (1U << block)) != 0; in amdgpu_ip_member_of_hwini()
192 adev->init_lvl = &amdgpu_init_minimal_xgmi; in amdgpu_set_init_level()
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/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
64 * In device fini, wait 10 minutes for user processes to be terminated after we kill them.
95 /* Default value for device reset trigger , an invalid value */
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/linux/init/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
8 - Re-run Kconfig when the compiler is updated
13 - Ensure full rebuild when the compiler is updated
14 include/linux/compiler-version.h contains this option in the comment
16 auto-generated dependency. When the compiler is updated, syncconfig
20 def_bool $(success,test "$(cc-name)" = GCC)
24 default $(cc-version) if CC_IS_GCC
28 def_bool $(success,test "$(cc-name)" = Clang)
32 default $(cc-version) if CC_IS_CLANG
36 def_bool $(success,test "$(as-name)" = GNU)
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/linux/kernel/trace/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 API, which will be used by other function-entry hooking
27 See Documentation/trace/ftrace-design.rst
32 See Documentation/trace/ftrace-design.rst
45 See Documentation/trace/ftrace-design.rst
62 This allows for use of ftrace_regs_get_argument() and
80 See Documentation/trace/ftrace-design.rst
85 See Documentation/trace/ftrace-design.rst
90 Arch supports the gcc options -pg with -mfentry
95 Arch supports the gcc options -pg with -mrecord-mcount and -nop-mcount
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/linux/Documentation/virt/uml/
H A Duser_mode_linux_howto_v2.rst1 .. SPDX-License-Identifier: GPL-2.0
16 release date 1991) and second virtualization platform for an x86 PC.
22 hardware emulation. In fact, it does not. As long as a virtualization
24 has a driver for, the devices do not need to emulate real hardware.
25 Most OSes today have built-in support for a number of "fake"
27 User Mode Linux takes this concept to the ultimate extreme - there
30 concepts which map onto something provided by the host - files, sockets,
36 The UML kernel is just a process running on Linux - same as any other
57 * You can run a usermode kernel as a non-root user (you may need to
58 arrange appropriate permissions for some devices).
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/linux/Documentation/process/
H A D2.Process.rst11 how the process works is required in order to be an effective part of it.
14 ---------------
16 The kernel developers use a loosely time-based release process, with a new
36 merging of patches for each release. At the beginning of each development
39 community) is merged into the mainline kernel. The bulk of changes for a
49 The merge window lasts for approximately two weeks. At the end of this
51 first of the "rc" kernels. For the kernel which is destined to be 5.6,
52 for example, the release which happens at the end of the merge window will
53 be called 5.6-rc1. The -rc1 release is the signal that the time to
61 As a general rule, if you miss the merge window for a given feature, the
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/linux/drivers/infiniband/hw/hfi1/
H A Dpcie.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2019 Intel Corporation.
27 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
37 * Both reset cases set the BAR back to initial state. For in hfi1_pcie_init()
43 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
49 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
53 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in hfi1_pcie_init()
60 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in hfi1_pcie_init()
90 * fields required to re-initialize after a chip reset, or for
111 return -EINVAL; in hfi1_pcie_ddinit()
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/linux/Documentation/filesystems/
H A Dresctrl.rst1 .. SPDX-License-Identifier: GPL-2.0
5 User Interface for Resource Control feature (resctrl)
9 :Authors: - Fenghua Yu <fenghua.yu@intel.com>
10 - Tony Luck <tony.luck@intel.com>
11 - Vikas Shivappa <vikas.shivappa@intel.com>
38 # mount -t resctrl resctrl [-o cdp[,cdpl2][,mba_MBps][,debug]] /sys/fs/resctrl
57 pseudo-locking is a unique way of using cache control to "pin" or
59 "Cache Pseudo-Locking".
64 For more details on the behavior of the interface during monitoring
81 The number of CLOSIDs which are valid for this
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/linux/Documentation/networking/
H A Dcan.rst2 SocketCAN - Controller Area Network
9 (Controller Area Network) for Linux. CAN is a networking technology
12 for Linux based on character devices, SocketCAN uses the Berkeley
20 .. _socketcan-motivation:
25 There have been CAN implementations for Linux before SocketCAN so the
27 implementations come as a device driver for some CAN hardware, they
29 functionality. Usually, there is only a hardware-specific device
31 receive raw CAN frames, directly to/from the controller hardware.
32 Queueing of frames and higher-level transport protocols like ISO-TP
34 character-device implementations support only one single process to
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/linux/include/uapi/linux/
H A Dkfd_ioctl.h16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
30 * - 1.1 - initial version
31 * - 1.3 - Add SMI events support
32 * - 1.4 - Indicate new SRAM EDC bit in device properties
33 * - 1.5 - Ad
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/linux/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2015-2018 Etnaviv Project
9 #include <linux/dma-fence.h>
10 #include <linux/dma-mapping.h>
32 { .name = "etnaviv-gpu,2d" },
42 struct etnaviv_drm_private *priv = gpu->drm->dev_private; in etnaviv_gpu_get_param()
46 *value = gpu->identity.model; in etnaviv_gpu_get_param()
50 *value = gpu->identity.revision; in etnaviv_gpu_get_param()
54 *value = gpu->identity.features; in etnaviv_gpu_get_param()
58 *value = gpu->identity.minor_features0; in etnaviv_gpu_get_param()
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