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/linux/Documentation/driver-api/fpga/
H A Dintro.rst4 The FPGA subsystem supports reprogramming FPGAs dynamically under
54 reprogramming FPGAs when device tree overlays are applied.
/linux/kernel/time/
H A Dhrtimer.c285 * the same CPU. No hassle vs. reprogramming the event source in switch_hrtimer_base()
606 * cpu_base::*expires_next right away, reprogramming logic would no longer
823 * function call will take care of the reprogramming in case the in retrigger_next_event()
893 /* If a deferred rearm is pending skip reprogramming the device */ in hrtimer_reprogram()
1136 * reprogram to zero. This is useful, when the context does a reprogramming
1193 * Remove the timer and force reprogramming when high in remove_hrtimer()
1195 * CPU. If we remove a timer on another CPU, reprogramming is in remove_hrtimer()
1197 * reprogramming happens in the interrupt handler. This is a in remove_hrtimer()
1298 * Reprogramming needs to be triggered, even if the next soft in hrtimer_update_softirq_timer()
1318 * CPU to optimize reprogramming o in hrtimer_prefer_local()
[all...]
H A Dtick-broadcast.c722 * it can avoid reprogramming the cpu local in tick_handle_oneshot_broadcast()
904 * reprogramming makes sure that the event in ___tick_broadcast_oneshot_control()
913 * avoid reprogramming and enforce that the in ___tick_broadcast_oneshot_control()
H A Dclockevents.c211 "CE: Reprogramming failure. Giving up\n"); in clockevents_increase_min_delta()
356 /* ktime_t based reprogramming for the broadcast hrtimer device */ in clockevents_program_event()
/linux/arch/arm/kernel/
H A Dvmlinux-xip.lds.S187 * situation when we are reprogramming MPU region we run on with
188 * something which doesn't cover reprogramming code itself, so as soon
/linux/drivers/firmware/microchip/
H A DKconfig9 Support for reprogramming PolarFire SoC from within Linux, using the
H A Dmpfs-auto-update.c3 * Microchip Polarfire SoC "Auto Update" FPGA reprogramming.
469 MODULE_DESCRIPTION("PolarFire SoC Auto Update FPGA reprogramming");
/linux/drivers/mtd/maps/
H A Dsc520cdp.c
/linux/arch/loongarch/kernel/
H A Dgenex.S30 * reprogramming. Fall through -- see handle_vint() below -- and have
/linux/drivers/parisc/
H A Dgsc.c157 /* ASP chip (svers 0x70) does not support reprogramming */ in gsc_set_affinity_irq()
/linux/drivers/media/i2c/
H A Dmax9271.h229 * communicate with local devices that do not support address reprogramming.
/linux/drivers/fpga/
H A Dfpga-region.c91 * reprogramming the region until the caller considers it safe to do so.
/linux/drivers/gpu/drm/
H A Ddrm_plane_helper.c230 * drm_mode_set_config_internal. We're reprogramming the same in drm_plane_helper_update_primary()
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max9286.yaml193 address reprogramming. The number of entries depends on the
/linux/drivers/pwm/
H A Dpwm-xilinx.c12 * reprogramming, but I think it would add complexity for little gain.
/linux/drivers/gpu/drm/i915/display/
H A Dintel_global_state.c358 * after the hardware reprogramming is done. in intel_atomic_global_state_setup_commit()
/linux/drivers/gpu/drm/pl111/
H A Dpl111_drv.c32 * - Read back hardware state at boot to skip reprogramming the
/linux/Documentation/timers/
H A Dno_hz.rst92 number of expensive clock-reprogramming operations.
/linux/arch/arm/mach-omap2/
H A Dio.c392 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate); in _omap2_init_reprogram_sdrc()
/linux/arch/arm/mm/
H A Dioremap.c416 * code in external memory. This is needed for reprogramming source
/linux/Documentation/devicetree/bindings/fpga/
H A Dfpga-region.yaml143 FPGA. After reprogramming is successful, the overlay is accepted into the live
/linux/drivers/cpufreq/
H A Dimx6q-cpufreq.c111 * reprogram PLL for frequency scaling. The procedure of reprogramming in imx6q_set_target()
/linux/fs/
H A Dtimerfd.c499 * We need to stop the existing timer before reprogramming in do_timerfd_settime()
/linux/drivers/pci/controller/dwc/
H A Dpcie-designware-ep.c905 * supported, so we avoid reprogramming the region on every MSI, in dw_pcie_ep_raise_msi_irq()
912 * mapping size changed. Reprogramming the iATU when there are in dw_pcie_ep_raise_msi_irq()
/linux/drivers/clk/qcom/
H A Dclk-cpu-8996.c36 * when we are reprogramming the PLL itself (for rate changes) when

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