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/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
41 -
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H A Dnetdev.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
9 -
11 name: xdp-act
12 render-max: true
14 -
19 -
23 -
24 name: ndo-xmit
27 -
28 name: xsk-zerocopy
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H A Dethtool.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
8 uapi-header: linux/ethtool_netlink_generated.h
11 -
12 name: udp-tunnel-type
13 enum-name:
15 entries: [ vxlan, geneve, vxlan-gpe ]
16 enum-cnt-name: __ethtool-udp-tunnel-type-cnt
17 render-max: true
18 -
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/linux/drivers/gpu/drm/xe/
H A Dxe_tuning.c1 // SPDX-License-Identifier: MIT
35 { XE_RTP_NAME("Tuning: L3 cache - media"),
45 { XE_RTP_NAME("Tuning: Compression Overfetch - media"),
54 { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3 - media"),
63 { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only - media"),
73 { XE_RTP_NAME("Tuning: Stateless compression control - media"),
82 { XE_RTP_NAME("Tuning: L3 RW flush all cache - media"),
93 ENGINE_CLASS(RENDER)),
101 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
111 XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
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H A Dxe_gt_freq.c1 // SPDX-License-Identifier: MIT
34 * device/tile#/gt#/freq0/<item>_freq *read-only* files:
35 * - act_freq: The actual resolved frequency decided by PCODE.
36 * - cur_freq: The current one requested by GuC PC to the PCODE.
37 * - rpn_freq: The Render Performance (RP) N level, which is the minimal one.
38 * - rpe_freq: The Render Performance (RP) E level, which is the efficient one.
39 * - rp0_freq: The Render Performance (RP) 0 level, which is the maximum one.
41 * device/tile#/gt#/freq0/<item>_freq *read-write* files:
42 * - min_freq: Min frequency request.
43 * - max_freq: Max frequency request.
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H A Dxe_guc_capture.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2024 Intel Corporation
45 * Book-keeping structure used to track read and write pointers
46 * as we extract error capture data from the GuC-log-buffer's
47 * error-capture region as a stream of dwords.
57 * struct __guc_capture_parsed_output - extracted error capture node
59 * A single unit of extracted error-capture output data grouped together
60 * at an engine-instance level. We keep these nodes in a linked list.
65 * A single set of 3 capture lists: a global-list
66 * an engine-class-list and an engine-instance list.
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/linux/Documentation/netlink/
H A Dgenetlink.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
3 ---
4 $id: http://kernel.org/schemas/netlink/genetlink-legacy.yaml#
5 $schema: https://json-schema.org/draft-07/schema
12 len-or-define:
14 pattern: ^[0-9A-Za-z_-]+( - 1)?$
16 len-or-limit:
17 # literal int or limit based on fixed-width type e.g. u8-min, u16-max, etc.
19 pattern: ^[su](8|16|32|64)-(min|max)$
26 required: [ name, doc, attribute-sets, operations ]
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/linux/drivers/gpu/drm/i915/gt/shaders/clear_kernel/
H A Dhsw.asm1 // SPDX-License-Identifier: MIT
10 * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
11 * 512 bytes of Render Cache.
20 * DW 1.0 - Block Offset to write Render Cache
21 * DW 1.1 [15:0] - Clear Word
22 * DW 1.2 - Delay iterations
23 * DW 1.3 - Enable Instrumentation (only for debug)
24 * DW 1.4 - Rsvd (intended for context ID)
25 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
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H A Divb.asm1 // SPDX-License-Identifier: MIT
10 * 2. Write 32x16 block of all "0" to render target buffer which indirectly clears
11 * 512 bytes of Render Cache.
20 * DW 1.0 - Block Offset to write Render Cache
21 * DW 1.1 [15:0] - Clear Word
22 * DW 1.2 - Delay iterations
23 * DW 1.3 - Enable Instrumentation (only for debug)
24 * DW 1.4 - Rsvd (intended for context ID)
25 * DW 1.5 - [31:16]:SliceCount, [15:0]:SubSlicePerSliceCount
26 * DW 1.6 - Rsvd MBZ (intended for Enable Wait on Total Thread Count)
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/linux/drivers/gpu/drm/v3d/
H A Dv3d_perfmon.c1 // SPDX-License-Identifier: GPL-2.0
13 …{"FEP", "FEP-valid-primitives-no-rendered-pixels", "[FEP] Valid primitives that result in no rende…
14 …{"FEP", "FEP-valid-primitives-rendered-pixels", "[FEP] Valid primitives for all rendered tiles (pr…
15 {"FEP", "FEP-clipped-quads", "[FEP] Early-Z/Near/Far clipped quads"},
16 {"FEP", "FEP-valid-quads", "[FEP] Valid quads"},
17 …{"TLB", "TLB-quads-not-passing-stencil-test", "[TLB] Quads with no pixels passing the stencil test…
18 …{"TLB", "TLB-quads-not-passing-z-and-stencil-test", "[TLB] Quads with no pixels passing the Z and …
19 …{"TLB", "TLB-quads-passing-z-and-stencil-test", "[TLB] Quads with any pixels passing the Z and ste…
20 {"TLB", "TLB-quads-with-zero-coverage", "[TLB] Quads with all pixels having zero coverage"},
21 …{"TLB", "TLB-quads-with-non-zero-coverage", "[TLB] Quads with any pixels having non-zero coverage"…
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/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_fwif_client.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
27 * Minimum PB = Base Pages + (NUM_TE_PIPES-1)*16K + (NUM_VCE_PIPES-1)*64K +
39 * Since the max of NUM_TE_PIPES and NUM_VCE_PIPES is 4, we have a hard limit
40 * of 4GB minus the Minimum PB. For convenience we take the smaller power-of-2
60 /* Indicates whether this render produces visibility results. */
66 /* Disable pixel merging for this render. */
70 /* Disallow compute overlapped with this render. */
153 * Holds the geometry/fragment fence value to allow the fragment partial render command
252 /* Stride IN BYTES for Z-Buffer in case of RTAs. */
254 /* Stride IN BYTES for S-Buffer in case of RTAs. */
H A Dpvr_rogue_fwif_sf.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
47 * - --- ---- ---- ---- ---- ---- ---- ----
48 * 0-11: id number
49 * 12-15: group id number
50 * 16-19: number of parameters
51 * 20-27: unused
52 * 28-30: active: identify SF packet, otherwise regular int32
80 "Kick 3D: FWCtx 0x%08.8x @ %d, RTD 0x%08x. Partial render:%d, CSW resume:%d, prio:%d" },
96 "Restart TA after partial render" },
98 "Resume TA without partial render" },
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H A Dpvr_rogue_fwif.h1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
42 /* String used in pvrdebug -h output */
140 /* Firmware per-DM HWR states */
147 /* DM need partial render cleanup before resuming processing */
155 /* DM was identified as over-running and causing HWR */
157 /* DM was innocently affected by another DM over-running which caused HWR */
270 /* Identify whether MC config is P-P or P-S */
274 /* per-os firmware shared data */
297 /* Firmware trace time-stamp field breakup */
303 /* Extra debug-info (16 bits) */
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_rps.c1 // SPDX-License-Identifier: MIT
43 return rps_to_gt(rps)->i915; in rps_to_i915()
48 return rps_to_gt(rps)->uncore; in rps_to_uncore()
55 return &gt_to_guc(gt)->slpc; in rps_to_slpc()
62 return intel_uc_uses_guc_slpc(&gt->uc); in rps_uses_slpc()
67 return mask & ~rps->pm_intrmsk_mbz; in rps_pm_sanitize_mask()
90 last = engine->stats.rps; in rps_timer()
91 engine->stats.rps = dt; in rps_timer()
99 last = rps->pm_timestamp; in rps_timer()
100 rps->pm_timestamp = timestamp; in rps_timer()
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H A Dintel_gt_regs.h1 /* SPDX-License-Identifier: MIT */
16 * lists of registers (where they're mixed in with other non-MCR registers)
18 * as non-multicast so we can place them on the same list, but we may want
90 * On GEN4, only the render ring INSTDONE exists and has a different
110 /* GM45+ chicken bits -- debug workaround bits that may be required
115 /* Disables pipelining of read flushes past the SF-WIZ interface.
116 * Required on all Ironlake steppings according to the B-Spec, but the
212 * - Power context is saved elsewhere (LLC or stolen)
213 * - Ring/execlist context is saved on SNB, not on IVB
214 * - Extended context size already includes render context size
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/linux/Documentation/driver-api/mtd/
H A Dspi-intel.rst2 Upgrading BIOS using spi-intel
14 The spi-intel driver makes it possible to read and write the SPI serial
16 any of them set, the whole MTD device is made read-only to prevent
18 contents as read-only but it can be changed from kernel command line,
22 might render the machine unbootable and requires special equipment like
25 Below are the steps how to upgrade MinnowBoard MAX BIOS directly from
28 1) Download and extract the latest Minnowboard MAX BIOS SPI image
31 2) Install mtd-utils package [2]. We need this in order to erase the SPI
33 name "mtd-utils".
67 Erasing 4 Kibyte @ 7ff000 -- 100 % complete
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/linux/scripts/
H A Dasn1_compiler.c1 // SPDX-License-Identifier: GPL-2.0-or-later
229 [DIRECTIVE_ENCODING_CONTROL] = "ENCODING-CONTROL",
253 _(MAX),
255 [DIRECTIVE_MINUS_INFINITY] = "MINUS-INFINITY",
265 [DIRECTIVE_PLUS_INFINITY] = "PLUS-INFINITY",
270 [DIRECTIVE_RELATIVE_OID] = "RELATIVE-OID",
325 clen = (dlen < token->size) ? dlen : token->size; in directive_compare()
327 //debug("cmp(%s,%s) = ", token->content, dir); in directive_compare()
329 val = memcmp(token->content, dir, clen); in directive_compare()
335 if (dlen == token->size) { in directive_compare()
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/linux/drivers/gpu/drm/vc4/
H A Dvc4_validate.c40 * user-submitted CL and writing the validated copy out to the memory
55 /** Return the width in pixels of a 64-byte microtile. */
73 /** Return the height in pixels of a 64-byte microtile. */
91 * size_is_lt() - Returns whether a miplevel of the given size will
108 struct vc4_dev *vc4 = exec->dev; in vc4_use_bo()
112 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4)) in vc4_use_bo()
115 if (hindex >= exec->bo_count) { in vc4_use_bo()
117 hindex, exec->bo_count); in vc4_use_bo()
120 obj = to_drm_gem_dma_obj(exec->bo[hindex]); in vc4_use_bo()
121 bo = to_vc4_bo(&obj->base); in vc4_use_bo()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_fb.c1 // SPDX-License-Identifier: MIT
6 #include <linux/dma-fence.h>
7 #include <linux/dma-resv.h>
23 #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a))
28 * the cache-line pairs. The compression state of the cache-line pair
29 * is specified by 2 bits in the CCS. Each CCS cache-line represents
30 * an area on the main surface of 16 x16 sets of 128 byte Y-tiled
31 * cache-line-pairs. CCS is always Y tiled."
59 * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
60 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
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/linux/sound/pci/lx6464es/
H A Dlx_defs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* -*- linux-c -*- *
16 * [ 44k - ( 44.1k + 48k ) / 2 ]
75 #define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
80 /* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */
130 PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
132 PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do
170 SF_XRUN = 0x20000000, /* the stream is un x-run state. */
281 #define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */
282 #define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */
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/linux/drivers/gpu/drm/amd/display/modules/freesync/
H A Dfreesync.c2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
36 /* Number of elements in the render times cache array */
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
72 core_freesync->dc = dc; in mod_freesync_create()
73 return &core_freesync->public; in mod_freesync_create()
119 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
120 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
127 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; in calc_max_hardware_v_total()
129 if (stream->ctx->dc->caps.vtotal_limited_by_fp2) { in calc_max_hardware_v_total()
130 max_hw_v_total -= stream->timing.v_front_porch + 1; in calc_max_hardware_v_total()
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/linux/drivers/video/fbdev/core/
H A Dfbcon.h2 * linux/drivers/video/console/fbcon.h -- Low level frame buffer based console driver
22 * This is the interface between the low-level console driver and the
23 * low-level frame buffer device
27 /* Filled in by the low-level console driver */
114 max_len = max(info->var.green.length, info->var.red.length); in mono_col()
115 max_len = max(info->var.blue.length, max_len); in mono_col()
130 if (vc->vc_can_do_color) in attr_col_ec()
131 return is_fg ? attr_fgcol(shift,vc->vc_video_erase_char) in attr_col_ec()
132 : attr_bgcol(shift,vc->vc_video_erase_char); in attr_col_ec()
138 is_mono01 = info->fix.visual == FB_VISUAL_MONO01; in attr_col_ec()
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/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c2 * SPDX-License-Identifier: MIT
4 * Copyright © 2011-2012 Intel Corporation
13 * supports contexts for the render ring.
19 * would happen if a client ran and piggy-backed off another clients GPU state.
27 * store GPU state, and thus allow GPU clients to not re-emit state (and
31 * The context life cycle is semi-complicated in that context BOs may live
44 * S0->S1: client creates a context
45 * S1->S2: client submits execbuf with context
46 * S2->S3: other clients submits execbuf with context
47 * S3->S1: context object was retired
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/linux/include/uapi/drm/
H A Damdgpu_drm.h1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
166 /* Flag that BO should be coherent across devices when using device-level
174 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */
267 #define AMDGPU_CTX_PRIORITY_UNSET -2048
268 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
269 #define AMDGPU_CTX_PRIORITY_LOW -512
378 /* SI-CI-VI: */
397 /* GFX9 - GFX11: */
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/linux/drivers/gpu/drm/
H A Ddrm_drv.c76 * A DRM device can provide several char-dev interfaces on the DRM-Major. Each
78 * of the device-driver, different interfaces are registered.
80 * Minors can be accessed via dev->$minor_name. This pointer is either
82 * valid. This means, DRM minors have the same life-time as the underlying
84 * registered and unregistered dynamically according to device-state.
96 return ERR_PTR(-EOPNOTSUPP); in drm_minor_get_xa()
104 return &dev->primary; in drm_minor_get_slot()
106 return &dev->render; in drm_minor_get_slot()
108 return &dev->accel; in drm_minor_get_slot()
118 WARN_ON(dev != minor->dev); in drm_minor_alloc_release()
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