Searched +full:rejection +full:- +full:60 +full:- +full:hz +full:- +full:enable (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/iio/temperature/ |
| H A D | max31865.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * max31865.c - Maxim MAX31865 RTD-to-Digital Converter sensor driver
43 static const char max31865_show_samp_freq[] = "50 60";
64 return spi_write_then_read(data->spi, ®, 1, data->buf, read_size); in max31865_read()
69 return spi_write(data->spi, data->buf, len); in max31865_write()
81 cfg = data->buf[0]; in enable_bias()
83 data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT; in enable_bias()
84 data->buf[1] = cfg | MAX31865_CFG_VBIAS; in enable_bias()
98 cfg = data->buf[0]; in disable_bias()
101 data->buf[0] = MAX31865_CFG_REG | MAX31865_RD_WR_BIT; in disable_bias()
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| /linux/drivers/iio/adc/ |
| H A D | ad7192.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2011-2015 Analog Devices Inc.
12 #include <linux/clk-provider.h>
36 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
37 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
38 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
39 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
40 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
41 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
42 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
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