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/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dregister-bit-led.txt1 Device Tree Bindings for Register Bit LEDs
3 Register bit leds are used with syscon multifunctional devices
4 where single bits in a certain register can turn on/off a
5 single LED. The register bit LEDs appear as children to the
10 Each LED is represented as a sub-node of the syscon device. Each
11 node's name represents the name of the corresponding LED.
13 LED sub-node properties:
16 - compatible : must be "register-bit-led"
17 - offset : register offset to the register controlling this LED
18 - mask : bit mask for the bit controlling this LED in the register
[all …]
H A Dregister-bit-led.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/register
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H A Dleds-bcm63138.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-bcm63138.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafał Miłecki <rafal@milecki.pl>
24 - items:
25 - enum:
26 - brcm,bcm4908-leds
27 - brcm,bcm6848-leds
28 - brcm,bcm6858-leds
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/freebsd/sys/contrib/device-tree/src/mips/mti/
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
36 cpu_intc: interrupt-controller {
37 compatible = "mti,cpu-interrupt-controller";
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/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
[all …]
H A Dti-lmu.txt6 ------ ---------------------------------
9 LM3633 Backlight, LED and fault monitor
14 - compatible: Should be one of:
20 - reg: I2C slave address.
28 - enable-gpios: A GPIO specifier for hardware enable pin.
29 - ramp-up-us: Current ramping from one brightness level to
31 Range from 2048 us - 117.44 s
32 - ramp-down-us: Current ramping from one brightness level to
34 Range from 2048 us - 117.44 s
35 - ti,brightness-resolution - This determines whether to use 8 bit brightness
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-motherboard.dtsi4 * Copyright (c) 2013-2014 ARM Ltd
11 mb_clk24mhz: clock-24000000 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "juno_mb:clk24mhz";
18 mb_clk25mhz: clock-25000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <25000000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dintegrator.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #address-cells = <1>;
8 #size-cells = <1>;
15 core-module@10000000 {
16 compatible = "arm,core-module-integrator", "syscon", "simple-mfd";
19 #address-cells = <1>;
20 #size-cells = <1>;
22 /* Use core module LED to indicate CPU load */
23 led@c,0 {
24 compatible = "register-bit-led";
[all …]
H A Darm-realview-eb.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-eb";
48 vmmc: regulator-vmmc {
49 compatible = "regulator-fixed";
50 regulator-name = "vmmc";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
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H A Dversatile-ab.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
6 compatible = "arm,versatile-ab";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
19 stdout-path = &uart0;
27 xtal24mhz: clock-24000000 {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
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H A Darm-realview-pbx.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-pbx";
49 vmmc: regulator-vmmc {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmc";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
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H A Darm-realview-pb1176.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb1176";
50 vmmc: regulator-vmmc {
51 compatible = "regulator-fixed";
52 regulator-name = "vmmc";
53 regulator-min-microvolt = <3300000>;
[all …]
H A Darm-realview-pb11mp.dts23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb11mp";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "arm,realview-smp";
60 next-level-cache = <&L2>;
[all …]
H A Dversatile-ab-ib2.dts1 // SPDX-License-Identifier: GPL-2.0
7 #include "versatile-ab.dts"
12 /* Special IB2 control register */
14 compatible = "arm,versatile-ib2-syscon", "syscon", "simple-mfd";
17 #address-cells = <1>;
18 #size-cells = <1>;
20 led@0,4 {
21 compatible = "register-bit-led";
25 label = "versatile-ib2:0";
26 linux,default-trigger = "heartbeat";
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/
H A Dintel-ixp42x-freecom-fsg-3.dts1 // SPDX-License-Identifier: ISC
3 * Device Tree file for the Freecom FSG-3 router.
8 /dts-v1/;
10 #include "intel-ixp42x.dtsi"
11 #include <dt-bindings/input/input.h>
14 model = "Freecom FSG-3";
15 compatible = "freecom,fsg-3", "intel,ixp42x";
16 #address-cells = <1>;
17 #size-cell
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmicrel.txt7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
12 KSZ8001: register 0x1e, bits 15..14
13 KSZ8041: register 0x1e, bits 15..14
14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
19 LAN8814: register EP5.0, bit 6
[all …]
/freebsd/sys/dev/isci/scil/
H A Dscic_sgpio.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
109 * register that is sent on the sLoad wire at the start of each
110 * bit stream.
113 * @param]in] vendor_specific_sequence - Vendor specific sequence set in the
114 * SGVSCR register.
124 * SGPBR(Programmable Blink Register). Will set identical patterns
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Darm,juno-fpga-apb-regs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
15 - const: arm,juno-fpga-apb-regs
16 - const: syscon
17 - const: simple-mfd
24 "#address-cells":
27 "#size-cells":
[all …]
/freebsd/sys/dev/e1000/
H A De1000_api.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 * e1000_init_mac_params - Initialize MAC function pointers
48 if (hw->mac.ops.init_params) { in e1000_init_mac_params()
49 ret_val = hw->mac.ops.init_params(hw); in e1000_init_mac_params()
56 ret_val = -E1000_ERR_CONFIG; in e1000_init_mac_params()
64 * e1000_init_nvm_params - Initialize NVM function pointers
74 if (hw->nvm.ops.init_params) { in e1000_init_nvm_params()
75 ret_val = hw->nvm.ops.init_params(hw); in e1000_init_nvm_params()
82 ret_val = -E1000_ERR_CONFIG; in e1000_init_nvm_params()
[all …]
H A De1000_mac.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * e1000_init_mac_ops_generic - Initialize MAC function pointers
45 * Setups up the function pointers to no-op functions
49 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_ops_generic()
53 mac->ops.init_params = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
54 mac->ops.init_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
55 mac->ops.reset_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
56 mac->ops.setup_physical_interface = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
57 mac->ops.get_bus_info = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
[all …]
/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
[all …]
/freebsd/sys/dev/mii/
H A Dciphyreg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
39 * Register definitions for the Cicada CS8201 10/100/1000 gigE copper
43 /* Command register */
47 #define CIPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
53 #define CIPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
59 /* Status register */
110 /* Antoneg expansion register */
126 /* Autoneg link partner next page receive register */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
23 * Register defintions for the Atheros AR5210/5110 MAC/Basedband
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
36 #define AR_CR 0x0008 /* Command register */
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe_x540.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
61 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_X540()
62 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_ops_X540()
63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_X540()
74 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; in ixgbe_init_ops_X540()
75 eeprom->ops.read = ixgbe_read_eerd_X540; in ixgbe_init_ops_X540()
76 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; in ixgbe_init_ops_X540()
77 eeprom->ops.write = ixgbe_write_eewr_X540; in ixgbe_init_ops_X540()
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300reg.h24 * MAC Register Map
32 /* MAC Control Register - only write values of 1 have effect */
37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt
40 /* MAC configuration and status register */
46 #define AR_CFG_SWRG 0x00000010 // byteswap register access data words
47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc)
55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */
62 /* Tx DMA Descriptor Pointer Threshold register */
65 /* Mac Interrupt rate threshold register */
70 /* MAC Global Interrupt enable register */
[all …]

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