reg\-offset (full) in projects: freebsd

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Searched +full:reg +full:- +full:offset (Results 1 – 25 of 1046) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A D	AArch64TargetStreamer.h	1 //===-- AArch64TargetStreamer.h - AArch64 Target Streamer ------- C++ ---===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 38 void emitNoteSection(unsigned Flags, uint64_t PAuthABIPlatform = -1, 39 uint64_t PAuthABIVersion = -1); 48 virtual void emitARM64WinCFISaveR19R20X(int Offset) {} in emitARM64WinCFISaveR19R20X() argument 49 virtual void emitARM64WinCFISaveFPLR(int Offset) {} in emitARM64WinCFISaveFPLR() argument 50 virtual void emitARM64WinCFISaveFPLRX(int Offset) {} in emitARM64WinCFISaveFPLRX() argument 51 virtual void emitARM64WinCFISaveReg(unsigned Reg, int Offset) {} in emitARM64WinCFISaveReg() argument 52 virtual void emitARM64WinCFISaveRegX(unsigned Reg, int Offset) {} in emitARM64WinCFISaveRegX() argument [all …]
H A D	AArch64WinCOFFStreamer.cpp	1 //===-- AArch64WinCOFFStreamer.cpp - ARM Target WinCOFF Streamer ----- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 67 // 2) take an offset: SEH_StackAlloc, SEH_SaveFPLR, SEH_SaveFPLR_X 68 // 3) take a register and an offset/size: all others 70 int Reg, int Offset) { in emitARM64WinUnwindCode() argument 75 auto Inst = WinEH::Instruction(UnwindCode, /Label=/nullptr, Reg, Offset); in emitARM64WinUnwindCode() 77 CurFrame->EpilogMap[CurrentEpilog].Instructions.push_back(Inst); in emitARM64WinUnwindCode() 79 CurFrame->Instructions.push_back(Inst); in emitARM64WinUnwindCode() 88 emitARM64WinUnwindCode(Op, -1, Size); in emitARM64WinCFIAllocStack() [all …]
H A D	AArch64ELFStreamer.cpp	1 //===- lib/MC/AArch64ELFStreamer.cpp - ELF Object Output for AArch64 ------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 //===----------------------------------------------------------------------===// 53 OS << "\t.variant_pcs\t" << Symbol->getName() << "\n"; in emitDirectiveVariantPCS() 59 void emitARM64WinCFISaveR19R20X(int Offset) override { in emitARM64WinCFISaveR19R20X() argument 60 OS << "\t.seh_save_r19r20_x\t" << Offset << "\n"; in emitARM64WinCFISaveR19R20X() 62 void emitARM64WinCFISaveFPLR(int Offset) override { in emitARM64WinCFISaveFPLR() argument 63 OS << "\t.seh_save_fplr\t" << Offset << "\n"; in emitARM64WinCFISaveFPLR() 65 void emitARM64WinCFISaveFPLRX(int Offset) override { in emitARM64WinCFISaveFPLRX() argument [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A D	VERegisterInfo.cpp	1 //===-- VERegisterInfo.cpp - VE Register Information ----------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 30 #define DEBUG_TYPE "ve-register-info" 40 switch (MF->getFunction().getCallingConv()) { in getCalleeSavedRegs() 80 VE::SX15, // Global offset table register in getReservedRegs() 82 VE::SX17, // Linkage-area register in getReservedRegs() 83 // sx18-sx33 are callee-saved registers in getReservedRegs() 84 // sx34-sx63 are temporary registers in getReservedRegs() [all …]
/freebsd/sys/arm64/arm64/
H A D	debug_monitor.c	1 /- 107 #define DBG_WB_READ(reg, num, val) do { \ argument 108 __asm __volatile("mrs %0, dbg" reg #num "_el1" : "=r" (val)); \ 111 #define DBG_WB_WRITE(reg, num, val) do { \ 112 __asm __volatile("msr dbg" reg #num "_el1, %0" :: "r" (val)); \ argument 115 #define READ_WB_REG_CASE(reg, num, offset, val) \ 116 case (num + offset): \ 117 DBG_WB_READ(reg, num, val); \ argument 120 #define WRITE_WB_REG_CASE(reg, nu 99 DBG_WB_READ(reg,num,val) global() argument 103 DBG_WB_WRITE(reg,num,val) global() argument 135 SWITCH_CASES_WRITE_WB_REG(reg,offset,val) global() argument 155 dbg_wb_read_reg(int reg,int n) dbg_wb_read_reg() argument 173 dbg_wb_write_reg(int reg,int n,uint64_t val) dbg_wb_write_reg() argument 340 uint64_t reg; dbg_find_free_slot() local [all...]
/freebsd/contrib/llvm-project/libunwind/src/
H A D	DwarfParser.hpp	1 //===----------------------------------------------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 10 //===----------------------------------------------------------------------===// 30 /// http://refspecs.linuxbase.org/LSB_3.1.0/LSB-Core-generic/LSB-Core-generic/ehframechpt.html 100 void checkSaveRegister(uint64_t reg, PrologInfo &initialState) { in checkSaveRegister() 101 if (!savedRegisters[reg].initialStateSaved) { in checkSaveRegister() 102 initialState.savedRegisters[reg] = savedRegisters[reg]; in checkSaveRegister() 103 savedRegisters[reg].initialStateSaved = true; in checkSaveRegister() 106 void setRegister(uint64_t reg, RegisterSavedWhere newLocation, in setRegister() 108 checkSaveRegister(reg, initialState); in setRegister() [all …]
/freebsd/contrib/llvm-project/llvm/tools/llvm-readobj/
H A D	ARMWinEHPrinter.cpp	1 //===-- ARMWinEHPrinter.cpp - Windows on ARM EH Data Printer ----- C++ -- 95 formatSymbol(StringRef Name,uint64_t Address,uint64_t Offset=0) formatSymbol() argument 254 getRelocatedSymbol(const COFFObjectFile &,const SectionRef & Section,uint64_t Offset) getRelocatedSymbol() argument 277 uint32_t Offset = CoffSym.getValue() + SymbolOffset - CS.getValue(); getPreferredSymbol() local 327 opcode_0xxxxxxx(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_0xxxxxxx() argument 338 opcode_10Lxxxxx(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_10Lxxxxx() argument 357 opcode_1100xxxx(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_1100xxxx() argument 369 opcode_11010Lxx(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11010Lxx() argument 386 opcode_11011Lxx(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11011Lxx() argument 403 opcode_11100xxx(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11100xxx() argument 417 opcode_111010xx(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_111010xx() argument 430 opcode_1110110L(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_1110110L() argument 444 opcode_11101110(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11101110() argument 460 opcode_11101111(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11101111() argument 478 opcode_11110101(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11110101() argument 493 opcode_11110110(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11110110() argument 508 opcode_11110111(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11110111() argument 521 opcode_11111000(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11111000() argument 536 opcode_11111001(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11111001() argument 549 opcode_11111010(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11111010() argument 564 opcode_11111011(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11111011() argument 571 opcode_11111100(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11111100() argument 578 opcode_11111101(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11111101() argument 585 opcode_11111110(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11111110() argument 592 opcode_11111111(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_11111111() argument 599 opcode_alloc_s(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_alloc_s() argument 609 opcode_save_r19r20_x(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_r19r20_x() argument 622 opcode_save_fplr(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_fplr() argument 632 opcode_save_fplr_x(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_fplr_x() argument 645 opcode_alloc_m(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_alloc_m() argument 658 opcode_save_regp(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_regp() argument 660 uint32_t Reg = ((OC[Offset] & 0x03) << 8); opcode_save_regp() local 673 opcode_save_regp_x(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_regp_x() argument 675 uint32_t Reg = ((OC[Offset] & 0x03) << 8); opcode_save_regp_x() local 694 opcode_save_reg(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_reg() argument 696 uint32_t Reg = (OC[Offset] & 0x03) << 8; opcode_save_reg() local 709 opcode_save_reg_x(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_reg_x() argument 711 uint32_t Reg = (OC[Offset] & 0x01) << 8; opcode_save_reg_x() local 726 opcode_save_lrpair(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_lrpair() argument 728 uint32_t Reg = (OC[Offset] & 0x01) << 8; opcode_save_lrpair() local 742 opcode_save_fregp(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_fregp() argument 744 uint32_t Reg = (OC[Offset] & 0x01) << 8; opcode_save_fregp() local 757 opcode_save_fregp_x(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_fregp_x() argument 759 uint32_t Reg = (OC[Offset] & 0x01) << 8; opcode_save_fregp_x() local 776 opcode_save_freg(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_freg() argument 778 uint32_t Reg = (OC[Offset] & 0x01) << 8; opcode_save_freg() local 791 opcode_save_freg_x(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_freg_x() argument 793 uint32_t Reg = ((OC[Offset + 1] & 0xE0) >> 5) + 8; opcode_save_freg_x() local 807 opcode_alloc_l(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_alloc_l() argument 820 opcode_setfp(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_setfp() argument 829 opcode_addfp(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_addfp() argument 841 opcode_nop(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_nop() argument 848 opcode_end(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_end() argument 855 opcode_end_c(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_end_c() argument 862 opcode_save_next(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_next() argument 873 opcode_save_any_reg(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_save_any_reg() argument 886 int Reg = OC[Offset + 1] & 0x1F; opcode_save_any_reg() local 950 opcode_trap_frame(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_trap_frame() argument 957 opcode_machine_frame(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_machine_frame() argument 965 opcode_context(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_context() argument 972 opcode_clear_unwound_to_call(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_clear_unwound_to_call() argument 980 opcode_pac_sign_lr(const uint8_t * OC,unsigned & Offset,unsigned Length,bool Prologue) opcode_pac_sign_lr() argument 990 decodeOpcodes(ArrayRef<uint8_t> Opcodes,unsigned Offset,bool Prologue) decodeOpcodes() argument 1028 uint64_t Offset = VA - SectionVA; dumpXDataRecord() local 1132 dumpUnpackedEntry(const COFFObjectFile & COFF,const SectionRef Section,uint64_t Offset,unsigned Index,const RuntimeFunction & RF) dumpUnpackedEntry() argument 1200 dumpPackedEntry(const object::COFFObjectFile & COFF,const SectionRef Section,uint64_t Offset,unsigned Index,const RuntimeFunction & RF) dumpPackedEntry() argument 1298 dumpPackedARM64Entry(const object::COFFObjectFile & COFF,const SectionRef Section,uint64_t Offset,unsigned Index,const RuntimeFunctionARM64 & RF) dumpPackedARM64Entry() argument 1433 uint64_t Offset = PDataEntrySize * Index; dumpProcedureDataEntry() local [all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A D	XCoreRegisterInfo.cpp	1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 38 #define DEBUG_TYPE "xcore-reg-info" 63 unsigned Reg, unsigned FrameReg, int Offset ) { in InsertFPImmInst() argument 70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg) in InsertFPImmInst() 72 .addImm(Offset) in InsertFPImmInst() 77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst() 79 .addImm(Offset) in InsertFPImmInst() [all …]
/freebsd/sys/contrib/device-tree/src/mips/mti/
H A D	sead3.dts	`1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 8 #include <dt-bindings/interrupt-controller/mips-gic.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 13 compatible = "mti,sead-3"; 14 model = "MIPS SEAD-3"; 17 stdout-path = "serial1:115200"; 33 reg = <0x0 0x08000000>; 36 cpu_intc: interrupt-controller { [all …]`
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A D	arm-realview-eb.dtsi	`23 #include <dt-bindings/interrupt-controller/irq.h> 24 #include <dt-bindings/gpio/gpio.h> 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "arm,realview-eb"; 44 reg = <0x00000000 0x08000000>; 48 vmmc: regulator-vmmc { 49 compatible = "regulator-fixed"; 50 regulator-name = "vmmc"; 51 regulator-min-microvolt = <3300000>; [all …]`
H A D	arm-realview-pb11mp.dts	`23 /dts-v1/; 24 #include <dt-bindings/interrupt-controller/irq.h> 25 #include <dt-bindings/gpio/gpio.h> 28 #address-cells = <1>; 29 #size-cells = <1>; 31 compatible = "arm,realview-pb11mp"; 48 reg = <0x70000000 0x20000000>; 52 #address-cells = <1>; 53 #size-cells = <0>; 54 enable-method = "arm,realview-smp"; [all …]`
H A D	arm-realview-pbx.dtsi	`23 #include <dt-bindings/interrupt-controller/irq.h> 24 #include <dt-bindings/gpio/gpio.h> 27 #address-cells = <1>; 28 #size-cells = <1>; 29 compatible = "arm,realview-pbx"; 45 reg = <0x00000000 0x08000000>; 49 vmmc: regulator-vmmc { 50 compatible = "regulator-fixed"; 51 regulator-name = "vmmc"; 52 regulator-min-microvolt = <3300000>; [all …]`
H A D	arm-realview-pb1176.dts	`23 /dts-v1/; 24 #include <dt-bindings/interrupt-controller/irq.h> 25 #include <dt-bindings/gpio/gpio.h> 28 #address-cells = <1>; 29 #size-cells = <1>; 31 compatible = "arm,realview-pb1176"; 46 reg = <0x00000000 0x08000000>; 50 vmmc: regulator-vmmc { 51 compatible = "regulator-fixed"; 52 regulator-name = "vmmc"; [all …]`
/freebsd/sys/dev/liquidio/base/
H A D	lio_mem_ops.c	50 mask = oct->fn_list.bar1_idx_read(oct, idx); in lio_toggle_bar1_swapmode() 52 oct->fn_list.bar1_idx_write(oct, idx, mask); in lio_toggle_bar1_swapmode() 60 lio_write_bar1_mem8(struct octeon_device oct, uint32_t reg, uint64_t val) in lio_write_bar1_mem8() argument 63 bus_space_write_1(oct->mem_bus_space[1].tag, in lio_write_bar1_mem8() 64 oct->mem_bus_space[1].handle, reg, val); in lio_write_bar1_mem8() 69 lio_read_bar1_mem32(struct octeon_device oct, uint32_t reg) in lio_read_bar1_mem32() argument 72 return (bus_space_read_4(oct->mem_bus_space[1].tag, in lio_read_bar1_mem32() 73 oct->mem_bus_space[1].handle, reg)); in lio_read_bar1_mem32() 77 lio_write_bar1_mem32(struct octeon_device *oct, uint32_t reg, uint32_t val) in lio_write_bar1_mem32() argument 80 bus_space_write_4(oct->mem_bus_space[1].tag, in lio_write_bar1_mem32() [all …]
/freebsd/contrib/llvm-project/lldb/include/lldb/Symbol/
H A D	UnwindPlan.h	1 //===-- UnwindPlan.h --------------------------------------------- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 19 #include "lldb/lldb-private.h" 23 // The UnwindPlan object specifies how to unwind out of a function - where this 24 // function saves the caller's register values before modifying them (for non- 29 // Most commonly, registers are saved on the stack, offset some bytes from the 63 undefined, // reg is not available, e.g. volatile reg 64 same, // reg is unchanged 65 atCFAPlusOffset, // reg = deref(CFA + offset) [all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A D	xgene.txt	1 Device Tree Clock bindings for APM X-Gene 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 8 - compatible : shall be one of the following: 9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock 10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock 11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock 12 "apm,xgene-device-clock" - for a X-Gene device clock 13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock 14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock 17 - reg : shall be the physical PLL register address for the pll clock. [all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/controller/
H A D	sysctrl.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...]`
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A D	RISCVMakeCompressible.cpp	`1 //===-- RISCVMakeCompressible.cpp - Make more instructions compressible ---===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 13 // 2. A base register + offset where the offset is too large to be compressed 43 // sw a1, -236(a2) 44 // sw a1, -240(a2) 45 // sw a1, -244(a2) 46 // sw a1, -248(a2) 47 // sw a1, -252(a2) 48 // sw a0, -256(a2) [all …]`
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A D	MipsDisassembler.cpp	1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 34 #define DEBUG_TYPE "mips-disassembler" 69 // Only present in MIPS-I and MIPS-II in hasCOP3() 182 static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, 186 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset, 194 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, 198 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, [all …]
/freebsd/sys/contrib/openzfs/module/zfs/
H A D	vdev_raidz_math_powerpc_altivec_common.h	1 // SPDX-License-Identifier: CDDL-1.0 10 * or https://opensource.org/licenses/CDDL-1.0. 24 * <romain.dolbeau@european-processor-initiative.eu> 33 #define VR0_(REG, ...) "%[w"#REG"]" argument 34 #define VR1_(_1, REG, ...) "%[w"#REG"]" argument 35 #define VR2_(_1, _2, REG, ...) "%[w"#REG"]" argument 36 #define VR3_(_1, _2, _3, REG, ...) "%[w"#REG"]" argument 37 #define VR4_(_1, _2, _3, _4, REG, ...) "%[w"#REG"]" argument 38 #define VR5_(_1, _2, _3, _4, _5, REG, ...) "%[w"#REG"]" argument 39 #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "%[w"#REG"]" argument [all …]
/freebsd/share/man/man9/
H A D	microseq.9	42 .Bl -enum -offset indent 69 In any other mode, drivers may be tri-stated by 74 This read-only register reflects the inputs on the parallel port interface. 76 .Bl -column "Bit" "Name" "Description" -compact 90 .Bl -column "Bit" "Name " "Description" -compact 108 .Bd -literal 111 #define MS_OP_RFETCH 2 /* rfetch <reg>, <mask>, <ptr> / 112 #define MS_OP_RSET 3 / rset <reg>, <mask>, <mask> / 113 #define MS_OP_RASSERT 4 / rassert <reg>, <mask> / 116 #define MS_OP_DBRA 7 / dbra <offset> */ [all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/elf-core/
H A D	RegisterContextPOSIXCore_arm64.cpp	1 //===-- RegisterContextPOSIXCore_arm64.cpp --------------------------------===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 14 #include "Plugins/Process/elf-core/ProcessElfCore.h" 15 #include "Plugins/Process/elf-core/RegisterUtilities.h" 82 llvm::Triple::OSType os = process->GetArchitecture().GetTriple().getOS(); in RegisterContextCorePOSIX_arm64() 84 AuxVector aux_vec(process->GetAuxvData()); in RegisterContextCorePOSIX_arm64() 102 m_register_info_up->GetTargetArchitecture().GetTriple(); in RegisterContextCorePOSIX_arm64() 105 if (m_register_info_up->IsSSVEPresent()) { in RegisterContextCorePOSIX_arm64() 113 if (m_sve_state != SVEState::Streaming && m_register_info_up->IsSVEPresent()) in RegisterContextCorePOSIX_arm64() [all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/hisilicon/
H A D	hisilicon.txt	2 ---------------------------------------------------- 5 - compatible = "hisilicon,hi3660"; 9 - compatible = "hisilicon,hi3660-hikey960", "hisilicon,hi3660"; 13 - compatible = "hisilicon,hi3670"; 17 - compatible = "hisilicon,hi3670-hikey970", "hisilicon,hi3670"; 21 - compatible = "hisilicon,hi3798cv200"; 25 - compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; 29 - compatible = "hisilicon,hi3620-hi4511"; 33 - compatible = "hisilicon,hi6220"; 37 - compatible = "hisilicon,hi6220-hikey", "hisilicon,hi6220"; [all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A D	LanaiRegisterInfo.cpp	1 //===-- LanaiRegisterInfo.cpp - Lanai Register Information ------- C++ --===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 11 //===----------------------------------------------------------------------===// 137 MachineFunction &MF = *MI.getParent()->getParent(); in eliminateFrameIndex() 140 bool HasFP = TFI->hasFP(MF); in eliminateFrameIndex() 145 int Offset = MF.getFrameInfo().getObjectOffset(FrameIndex) + in eliminateFrameIndex() local 151 Offset += MF.getFrameInfo().getStackSize(); in eliminateFrameIndex() 162 // If the offset is small enough to fit in the immediate field, directly in eliminateFrameIndex() 165 if ((isSPLSOpcode(MI.getOpcode()) && !isInt<10>(Offset)) \|\| in eliminateFrameIndex() [all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A D	CFIInstrInserter.cpp	1 //===------ CFIInstrInserter.cpp - Insert additional CFI instructions -----===// 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 7 //===----------------------------------------------------------------------===// 10 /// blocks. CFA information is information about offset and register set by CFI 15 /// don't. CFI instructions are inserted if basic blocks have incorrect offset 16 /// or register set by previous blocks, as a result of a non-linear layout of 18 //===----------------------------------------------------------------------===// 31 static cl::opt<bool> VerifyCFI("verify-cfiinstrs", 70 /// Value of cfa offset valid at basic block entry. 71 int64_t IncomingCFAOffset = -1; [all …]

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