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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-hid-picolcd1 What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<p…
3 Contact: Bruno Prémont <bonbons@linux-vserver.org>
11 the non-active mode names listed when read.
18 What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<p…
20 Contact: Bruno Prémont <bonbons@linux-vserver.org>
28 What: /sys/bus/usb/devices/<busnum>-<devnum>:<config num>.<interface num>/<hid-bus>:<vendor-id>:<p…
30 Contact: Bruno Prémont <bonbons@linux-vserver.org>
31 Description: Make it possible to adjust defio refresh rate.
33 Reading: returns list of available refresh rates (expressed in Hz),
34 the active refresh rate being enclosed in brackets ('[' and ']')
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/linux/Documentation/devicetree/bindings/auxdisplay/
H A Dholtek,ht16k33.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robin van der Gracht <robin@protonic.nl>
13 - $ref: /schemas/input/matrix-keymap.yaml#
18 - items:
19 - enum:
20 - adafruit,3108 # 0.56" 4-Digit 7-Segment FeatherWing Display (Red)
21 - adafruit,3130 # 0.54" Quad Alphanumeric FeatherWing Display (Red)
22 - const: holtek,ht16k33
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/linux/Documentation/fb/
H A Duvesafb.rst2 uvesafb - A Generic Driver for VBE2+ compliant video cards
6 ---------------
30 --------------------------
36 - Lack of any type of acceleration.
37 - A strict and limited set of supported video modes. Often the native
38 or most optimal resolution/refresh rate for your setup will not work
42 ratio, which is what most BIOS-es are limited to.
43 - Adjusting the refresh rate is only possible with a VBE 3.0 compliant
44 Video BIOS. Note that many nVidia Video BIOS-es claim to be VBE 3.0
45 compliant, while they simply ignore any refresh rate settings.
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H A Dmodedb.rst9 - one routine to probe for video modes, which can be used by all frame buffer
11 - one generic video mode database with a fair amount of standard videomodes
13 - the possibility to supply your own mode database for graphics hardware that
14 needs non-standard modes, like amifb and Mac frame buffer drivers (which
23 <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
24 <name>[-<bpp>][@<refresh>]
26 with <xres>, <yres>, <bpp> and <refresh> decimal numbers and <name> a string.
31 - NSTC: 480i output, with the CCIR System-M TV mode and NTSC color encoding
32 - NTSC-J: 480i output, with the CCIR System-M TV mode, the NTSC color
34 - PAL: 576i output, with the CCIR System-B TV mode and PAL color encoding
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H A Dintel810.rst20 - Intel 810
21 - Intel 810E
22 - Intel 810-DC100
23 - Intel 815 Internal graphics only, 100Mhz FSB
24 - Intel 815 Internal graphics only
25 - Intel 815 Internal graphics and AGP
30 - Choice of using Discrete Video Timings, VESA Generalized Timing
33 - Supports a variable range of horizontal and vertical resolution and
34 vertical refresh rates if the VESA Generalized Timing Formula is
37 - Supports color depths of 8, 16, 24 and 32 bits per pixel
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H A Dvesafb.rst2 vesafb - Generic graphic framebuffer driver
20 * You can run XF68_FBDev on top of /dev/fb0 (=> non-accelerated X11
22 * Most important: boot logo :-)
33 Documentation/admin-guide/svga.rst for details.
81 "vga=mode-number" you have to transform the numbers to decimal.
88 XF68_FBDev should work just fine, but it is non-accelerated. Running
89 another (accelerated) X-Server like XF86_SVGA might or might not work.
90 It depends on X-Server and graphics board.
92 The X-Server must restore the video mode correctly, else you end up
96 Refresh rates
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/linux/drivers/gpu/drm/amd/display/modules/freesync/
H A Dfreesync.c2 * Copyright 2016-2023 Advanced Micro Devices, Inc.
34 /* Refresh rate ramp at a fixed rate of 65 Hz/second */
38 /* Threshold to exit/exit BTR (to avoid frequent enter-exits at the lower limit) */
42 /* Threshold to exit fixed refresh rate */
44 /* Number of consecutive frames to check before entering/exiting fixed refresh */
72 core_freesync->dc = dc; in mod_freesync_create()
73 return &core_freesync->public; in mod_freesync_create()
119 * 10000) * stream->timing.h_total, in calc_duration_in_us_from_v_total()
120 stream->timing.pix_clk_100hz)); in calc_duration_in_us_from_v_total()
127 unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; in calc_max_hardware_v_total()
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/linux/drivers/video/fbdev/core/
H A Dfbcvt.c2 * linux/drivers/video/fbcvt.c - VESA(TM) Coordinated Video Timings
38 u32 refresh; member
75 u32 num = 1000000000/cvt->f_refresh; in fb_cvt_hperiod()
78 if (cvt->flags & FB_CVT_FLAG_REDUCED_BLANK) { in fb_cvt_hperiod()
79 num -= FB_CVT_RB_MIN_VBLANK * 1000; in fb_cvt_hperiod()
80 den = 2 * (cvt->yres/cvt->interlace + 2 * cvt->v_margin); in fb_cvt_hperiod()
82 num -= FB_CVT_MIN_VSYNC_BP * 1000; in fb_cvt_hperiod()
83 den = 2 * (cvt->yres/cvt->interlace + cvt->v_margin * 2 in fb_cvt_hperiod()
84 + FB_CVT_MIN_VPORCH + cvt->interlace/2); in fb_cvt_hperiod()
93 u32 c_prime = (FB_CVT_GTF_C - FB_CVT_GTF_J) * in fb_cvt_ideal_duty_cycle()
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H A Dfbmon.c11 * Copyright (C) 1991-2002 SciTech Software, Inc. All rights reserved.
14 * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
65 /* DEC FR-PCXAV-YZ */
96 while (i-- && (*--s == 0x20)) *s = 0; in copy_string()
243 b[9] = 17; /* pixclock - 170 MHz*/ in fix_edid()
251 for (i = 0; i < EDID_LENGTH - 1; i++) in fix_edid()
254 edid[127] = 256 - csum; in fix_edid()
297 specs->manufacturer[0] = ((block[0] & 0x7c) >> 2) + '@'; in parse_vendor_block()
298 specs->manufacturer[1] = ((block[0] & 0x03) << 3) + in parse_vendor_block()
300 specs->manufacturer[2] = (block[1] & 0x1f) + '@'; in parse_vendor_block()
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/linux/arch/m68k/include/asm/
H A DMC68EZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
53 * 0xFFFFF1xx -- Chip-Select logic
84 #define CSA_EN 0x0001 /* Chip-Select Enable */
85 #define CSA_SIZ_MASK 0x000e /* Chip-Select Size */
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H A DMC68VZ328.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
55 * 0xFFFFF1xx -- Chip-Select logic
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/linux/arch/arm/mach-omap2/
H A Dsdrc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2008, 2012 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation
55 * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate
56 * @rate: SDRC clock rate (in Hz)
57 * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate
58 * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate
59 * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate
60 * @mr: Value to program to SDRC_MR for this rate
62 * This structure holds a pre-computed set of register values for the
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/linux/drivers/staging/sm750fb/
H A Dreadme4 - dual display
5 - 2D acceleration
6 - 16MB integrated video memory
10 Use 1280,8bpp index color and 60 hz mode:
11 insmod ./sm750fb.ko g_option="1280x1024-8@60"
23 1) if you build the driver with built-in method, the parameter
33 refresh rate, kernel driver will defaulty use 16bpp and 60hz
37 and this driver will use fb1, fb2. In that case, you need to configure your X-server
/linux/drivers/memory/tegra/
H A Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
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/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-enumstd.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_ENUMSTD - VIDIOC_SUBDEV_ENUMSTD - Enumerate supported video standards
52 .. flat-table:: struct v4l2_standard
53 :header-rows: 0
54 :stub-columns: 0
57 * - __u32
58 - ``index``
59 - Number of the video standard, set by the application.
60 * - :ref:`v4l2_std_id <v4l2-std-id>`
61 - ``id``
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/linux/drivers/memory/
H A Djedec_ddr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
64 /* Refresh rate in nano-seconds */
105 /* MR4 SDRAM Refresh Rate field values */
207 * -ENOENT if info unavailable.
223 * are in Hz.
/linux/drivers/video/fbdev/
H A Dcontrolfb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
52 struct preg hperiod; /* horiz period - 2 */
59 struct preg hserr; /* horiz period - horiz sync len */
67 struct preg rfrcnt; /* refresh count */
85 unsigned hperiod; /* horiz period - 2 */
92 unsigned hserr; /* horiz period - horiz sync len */
96 * Dot clock rate is
120 {{-1,-1}}, /* 512x384, 60Hz interlaced (NTSC) */
121 {{-1,-1}}, /* 512x384, 60Hz */
122 {{-1,-1}}, /* 640x480, 50Hz interlaced (PAL) */
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H A Dacornfb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1998-2001 Russell King
14 * - Blanking 8bpp displays with VIDC
26 #include <linux/dma-mapping.h>
32 #include <asm/mach-types.h>
68 }, { /* Hi-res mono */
114 struct fb_var_screeninfo *var = &info->var; in acornfb_set_timing()
122 vidc.h_sync_width = var->hsync_len - 8; in acornfb_set_timing()
123 vidc.h_border_start = vidc.h_sync_width + var->left_margin + 8 - 12; in acornfb_set_timing()
124 vidc.h_display_start = vidc.h_border_start + 12 - 18; in acornfb_set_timing()
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/linux/include/drm/
H A Ddrm_modes.h3 * Copyright © 2007-2008 Dave Airlie
4 * Copyright © 2007-2008 Intel Corporation
46 * enum drm_mode_status - hardware support status of a mode
129 MODE_STALE = -3,
130 MODE_BAD = -2,
131 MODE_ERROR = -1
142 * DRM_MODE_RES_MM - Calculates the display size from resolution and DPI
157 * DRM_MODE_INIT - Initialize display mode
158 * @hz: Vertical refresh rate in Hertz
165 * refresh rate, resolution and physical size.
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/linux/drivers/video/fbdev/kyro/
H A Dfbdev.c49 /* 640x480, 16bpp @ 60 Hz */
59 .height = -1,
60 .width = -1,
93 /* 640x350 @ 85Hz */
98 /* 640x400 @ 85Hz */
103 /* 720x400 @ 85Hz */
108 /* 640x480 @ 60Hz */
113 /* 640x480 @ 72Hz */
118 /* 640x480 @ 75Hz */
123 /* 640x480 @ 85Hz */
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/linux/drivers/pwm/
H A Dpwm-sophgo-sg2042.c1 // SPDX-License-Identifier: GPL-2.0
9 * - After reset, the output of the PWM channel is always high.
11 * - When HLPERIOD or PERIOD is reconfigured, PWM will start to
14 * - When PERIOD and HLPERIOD is set to 0, the PWM wave output will
16 * - SG2044 supports both polarities, SG2042 only normal polarity.
18 * [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM
52 * struct sg2042_pwm_ddata - private driver data
54 * @clk_rate_hz: rate of base clock in HZ
72 void __iomem *base = ddata->base; in pwm_sg2042_config()
89 period_ticks = min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->period, NSEC_PER_SEC), U32_MAX); in pwm_sg2042_set_dutycycle()
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/linux/drivers/devfreq/
H A Dimx8m-ddrc.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/clk-provider.h>
14 #include <linux/arm-smccc.h>
27 unsigned long rate; member
40 * +----------+ |\ +------+
41 * | dram_pll |-------|M| dram_core | |
42 * +----------+ |U|---------->| D |
43 * /--|X| | D |
46 * +---------+ | |
48 * +---------+ | |
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/linux/drivers/gpu/drm/
H A Ddrm_modes.c2 * Copyright © 1997-2003 by The XFree86 Project, Inc.
4 * Copyright © 2007-2008 Intel Corporation
6 * Copyright 2005-2006 Luc Verhaegen
53 * drm_mode_debug_printmodeline - print a mode to dmesg
65 * drm_mode_create - create a new display mode
87 * drm_mode_destroy - remove a mode
103 * drm_mode_probed_add - add a mode to a connector's probed_mode list
114 WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex)); in drm_mode_probed_add()
116 list_add_tail(&mode->head, &connector->probed_modes); in drm_mode_probed_add()
121 DRM_MODE_ANALOG_NTSC, /* 525 lines, 60Hz */
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright (C) 2015-2020 Advanced Micro Devices, Inc. All rights reserved.
100 * struct dm_compressor_info - Buffer info used by frame buffer compression
114 * struct dmub_hpd_work - Handle time consuming work in low priority outbox IRQ
127 * struct vblank_control_work - Work data for vblank control
143 * struct idle_workqueue - Work data for periodic action in idle
157 * struct vupdate_offload_work - Work data for offloading task from vupdate handler
173 * struct amdgpu_dm_luminance_data - Custom luminance data
175 * @input_signal: Input signal in range 0-255
183 * struct amdgpu_dm_backlight_caps - Information about backlight
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/linux/drivers/auxdisplay/
H A Dht16k33.c1 // SPDX-License-Identifier: GPL-2.0
30 #include "line-display.h"
140 uint8_t data = REG_DISPLAY_SETUP | REG_DISPLAY_SETUP_ON | priv->blink; in ht16k33_display_on()
142 return i2c_smbus_write_byte(priv->client, data); in ht16k33_display_on()
147 return i2c_smbus_write_byte(priv->client, REG_DISPLAY_SETUP); in ht16k33_display_off()
156 priv->blink = REG_DISPLAY_SETUP_BLINK_OFF; in ht16k33_brightness_set()
164 return i2c_smbus_write_byte(priv->client, in ht16k33_brightness_set()
165 REG_BRIGHTNESS | (brightness - 1)); in ht16k33_brightness_set()
198 err = i2c_smbus_write_byte(priv->client, in ht16k33_blink_set()
204 priv->blink = blink; in ht16k33_blink_set()
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