Searched +full:reference +full:- +full:doubler +full:- +full:enable (Results 1 – 5 of 5) sorted by relevance
4 - compatible: Should be one of7 - reg: SPI chip select numbert for the device8 - spi-max-frequency: Max SPI frequency to use (< 20000000)9 - clocks: From common clock binding. Clock is phandle to clock for10 ADF435x Reference Clock (CLKIN).13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).16 - adi,power-up-frequency: If set in Hz the PLL tunes to18 - adi,reference-div-factor: If set the driver skips dynamic calculation20 - adi,reference-doubler-enable: Enables reference doubler.[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Michael Hennerich <michael.hennerich@analog.com>15 - adi,adf435016 - adi,adf435121 spi-max-frequency:26 description: Clock to provide CLKIN reference clock signal.28 clock-names:31 '#clock-cells':[all …]
121 ahp->ah_hwp = HAL_TRUE_CHIP; in ar9300_attach_hw_platform()196 * Mask used to construct AAD for CCMP-AES in ar9300_init_mfp()197 * Cisco spec defined bits 0-3 as mask in ar9300_init_mfp()226 centers->ctl_center = centers->ext_center = in ar9300_get_channel_centers()227 centers->synth_center = ichan->channel; in ar9300_get_channel_centers()238 centers->synth_center = ichan->channel + HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()241 centers->synth_center = ichan->channel - HT40_CHANNEL_CENTER_SHIFT; in ar9300_get_channel_centers()242 extoff = -1; in ar9300_get_channel_centers()245 centers->ctl_center = in ar9300_get_channel_centers()246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); in ar9300_get_channel_centers()[all …]
12 A-b-c book13 A-b-c method14 abdomino-uterotomy15 Abdul-baha16 a-be20 able-bodied21 able-bodiedness22 able-minded23 able-mindedness27 Abor-miri[all …]
57268 doubler61459 enable99810 Jean-Christophe99811 Jean-Pierre165564 reference