Home
last modified time | relevance | path

Searched +full:reference +full:- +full:div2 +full:- +full:enable (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
10 ADF435x Reference Clock (CLKIN).
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
[all …]
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
26 description: Clock to provide CLKIN reference clock signal.
28 clock-names:
31 '#clock-cells':
[all …]
/freebsd/sys/arm/freescale/imx/
H A Dimx6_ssi.c1 /*-
30 * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual,
60 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
62 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
78 #define SCR_RE (1 << 2) /* Receive Enable. */
79 #define SCR_TE (1 << 1) /* Transmit Enable. */
80 #define SCR_SSIEN (1 << 0) /* SSI Enable */
82 #define SSI_SIER 0x18 /* Interrupt Enable Register */
83 #define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */
84 #define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
294 /** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */
458 /** @brief PLLC4 VCO followed by DIV2 path */
842 /** @brief VPLL0 reference clock */
848 /** @brief NVDISPLAY_P0_CLK reference select */
890 /** @brief output of fixed (DIV2) MC HUB divider */
/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
73 … 0x003818UL //Access:RW DataWidth:0x6 // Statistic mask enable Bit5 : Mask Messa…
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
98 … (0x1<<0) // I/O space access enable. There are no I/O…
100 … (0x1<<1) // Memory space access enable.
[all …]