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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
[all …]
H A Dfsl,imx8qm-hsio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
21 - description: HSIO CSR of the controller bound to the PHY
[all …]
H A Dimg,pistachio-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/img,pistachio-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Bresticker <abrestic@chromium.org>
14 const: img,pistachio-usb-phy
19 clock-names:
21 - const: usb_phy
23 '#phy-cells':
26 phy-supply:
[all …]
H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3528-naneng-combphy
16 - rockchip,rk3562-naneng-combphy
17 - rockchip,rk3568-naneng-combphy
18 - rockchip,rk3576-naneng-combphy
19 - rockchip,rk3588-naneng-combphy
[all …]
/linux/arch/mips/boot/dts/cavium-octeon/
H A Ddlink_dsr-500n-1000n.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device tree source for D-Link DSR-500N/1000N (common parts).
13 phy8: ethernet-phy@8 {
15 compatible = "ethernet-phy-ieee802.3-c22";
22 fixed-link {
24 full-duplex;
28 fixed-link {
30 full-duplex;
34 phy-handle = <&phy8>;
47 refclk-frequency = <12000000>;
[all …]
H A Dubnt_e100.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device tree source for EdgeRouter Lite.
15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
32 phy-handle = <&phy7>;
33 rx-delay = <0>;
[all …]
/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
12 description: |-
13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Dintel_cdclk.c2 * Copyright © 2006-2017 Intel Corporation
82 * - We have the CDCLK PLL, which generates an output clock based on a
84 * - The CD2X Divider, which divides the output of the PLL based on a
85 * divisor selected from a set of pre-defined choices.
86 * - The CD2X Squasher, which further divides the output based on a
89 * - And, finally, a fixed divider that divides the output frequency by 2.
108 * - Full PLL disable + re-enable with new VCO frequency. Pipes must be inactive.
109 * - CD2X divider update. Single pipe can be active as the divider update
111 * - Crawl the PLL smoothly to the new VCO frequency. Pipes can be active.
112 * - Squash waveform update. Pipes can be active.
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos4412-odroidu3.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel's Exynos4412 based ODROID-U3 board device tree source
7 * Device tree source file for Hardkernel's ODROID-U3 board which is based
11 /dts-v1/;
12 #include <dt-bindings/leds/common.h>
13 #include "exynos4412-odroid-common.dtsi"
14 #include "exynos4412-prime.dtsi"
17 model = "Hardkernel ODROID-U3 board based on Exynos4412";
18 compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4";
29 vbus_otg_reg: regulator-1 {
[all …]
H A Dexynos5410-odroidxu.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU board device tree source
10 /dts-v1/;
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos54xx-odroidxu-leds.dtsi"
20 compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
34 stdout-path = "serial2:115200n8";
[all …]
/linux/sound/soc/codecs/
H A Dcs530x.c1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2024-2025 Cirrus Logic, Inc. and
26 "vdd-a",
27 "vdd-io",
136 struct regmap *regmap = cs530x->regmap; in cs530x_put_volsw_vu()
154 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1270, 50, 0);
157 "Min Phase Slow Roll-off",
158 "Min Phase Fast Roll-off",
159 "Linear Phase Slow Roll-off",
160 "Linear Phase Fast Roll-off",
[all …]
H A Darizona.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arizona.c - Wolfson Arizona class device shared support
68 dev_err(_fll->arizona->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
70 dev_warn(_fll->arizona->de
1282 int ref, div, refclk; arizona_set_opclk() local
1366 arizona_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir) arizona_set_sysclk() argument
2330 arizona_apply_fll(struct arizona * arizona,unsigned int base,struct arizona_fll_cfg * cfg,int source,bool sync) arizona_apply_fll() argument
2555 arizona_set_fll_refclk(struct arizona_fll * fll,int source,unsigned int Fref,unsigned int Fout) arizona_set_fll_refclk() argument
2579 arizona_set_fll(struct arizona_fll * fll,int source,unsigned int Fref,unsigned int Fout) arizona_set_fll() argument
[all...]
H A Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
20 #include <linux/irqchip/irq-madera.h>
24 #include <sound/madera-pdata.h>
26 #include <dt-bindings/sound/madera.h>
145 dev_err(_fll->madera->de
2508 int ref, div, refclk; madera_set_opclk() local
2628 madera_set_outclk(struct snd_soc_component * component,unsigned int source,unsigned int freq) madera_set_outclk() argument
2680 madera_set_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir) madera_set_sysclk() argument
3716 madera_write_fll(struct madera * madera,unsigned int base,struct madera_fll_cfg * cfg,int source,bool sync,int gain) madera_write_fll() argument
4123 madera_set_fll_syncclk(struct madera_fll * fll,int source,unsigned int fref,unsigned int fout) madera_set_fll_syncclk() argument
4142 madera_set_fll_refclk(struct madera_fll * fll,int source,unsigned int fref,unsigned int fout) madera_set_fll_refclk() argument
4332 madera_set_fll_ao_refclk(struct madera_fll * fll,int source,unsigned int fin,unsigned int fout) madera_set_fll_ao_refclk() argument
4654 madera_fllhj_set_refclk(struct madera_fll * fll,int source,unsigned int fin,unsigned int fout) madera_fllhj_set_refclk() argument
[all...]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn20/
H A Ddcn20_dccg.c36 (dccg_dcn->regs->reg)
40 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
43 dccg_dcn->base.ctx
45 dccg->ctx->logger
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
57 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
88 // DCN20 has never been validated for non-xtalin as reference in dccg2_get_dccg_ref_freq()
90 // frequency a non-xtalin source is. in dccg2_get_dccg_ref_freq()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dinno-hdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Zheng Yang <zhengyang@rock-chips.com>
5 * Yakir Yang <ykk@rock-chips.com>
398 struct clk *refclk; member
416 * Cb = -0.291G - 0.148R + 0.439B + 128
418 * Cr = -0.368G + 0.439R - 0.071B + 128
427 * Cb = - 0.338G - 0.101R + 0.439B + 128
429 * Cr = - 0.399G + 0.439R - 0.040B + 128
438 * R' = R x (235-16)/255 + 16;
439 * G' = G x (235-16)/255 + 16;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgt215.c45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
66 /* refclk for the 0xe8xx plls is a fixed frequency */ in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
122 /* no post-divider on these.. in read_pll()
123 * XXX: it looks more like two post-"dividers" that in read_pll()
[all …]
H A Dmcp77.c44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll()
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
91 return device->crystal; in mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; in mcp77_clk_read()
97 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; in mcp77_clk_read()
100 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); in mcp77_clk_read()
102 case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); in mcp77_clk_read()
[all …]
H A Dnv50.c34 struct nvkm_device *device = clk->base.subdev.device; in read_div()
35 switch (device->chipset) { in read_div()
54 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_src()
55 struct nvkm_device *device = subdev->device; in read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
60 switch (device->chipset) { in read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); in read_pll_src()
104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll_src()
127 struct nvkm_subdev *subdev = &clk->base.subdev; in read_pll_ref()
128 struct nvkm_device *device = subdev->device; in read_pll_ref()
[all …]
H A Dgf100.c51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
75 sclk = device->crystal; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
107 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6q-bosch-acc.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Support for the i.MX6-based Bosch ACC board.
8 * Copyright (C) 2019-2021 Bosch Thermotechnik GmbH, Matthias Winker <matthias.winker@bosch.com>
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/leds/common.h>
20 compatible = "bosch,imx6q-acc", "fsl,imx6q";
37 backlight_lvds: backlight-lvds {
38 compatible = "pwm-backlight";
40 brightness-levels = <0 61 499 1706 4079 8022 13938 22237 33328 47623 65535>;
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8m-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on()
85 if (imx8_phy->tx_deemph_gen1) in imx8_pcie_phy_power_on()
86 writel(imx8_phy->tx_deemph_gen1, in imx8_pcie_phy_power_on()
87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on()
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779a0-falcon-cpu.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CPU board
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
16 compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
30 stdout-path = "serial0:115200n8";
34 compatible = "gpio-keys";
36 pinctrl-0 = <&keys_pins>;
37 pinctrl-names = "default";
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-motherboard.dtsi4 * Copyright (c) 2013-2014 ARM Ltd
11 mb_clk24mhz: clock-24000000 {
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <24000000>;
15 clock-output-names = "juno_mb:clk24mhz";
18 mb_clk25mhz: clock-25000000 {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <25000000>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm850-lenovo-yoga-c630.dts1 // SPDX-License-Identifier: BSD-3-Clause
8 /dts-v1/;
10 #include <dt-bindings/input/gpio-keys.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
13 #include <dt-bindings/sound/qcom,q6afe.h>
14 #include <dt-bindings/sound/qcom,q6asm.h>
16 #include "sdm845-wcd9340.dtsi"
24 /delete-node/ &ipa_fw_mem;
25 /delete-node/ &ipa_gsi_mem;
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234-p3768-0000+p3767.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/linux-event-codes.h>
4 #include <dt-bindings/input/gpio-keys.h>
6 #include "tegra234-p3767.dtsi"
17 stdout-path = "serial0:115200n8";
22 compatible = "nvidia,tegra194-hsuart";
23 reset-names = "serial";
28 compatible = "nvidia,tegra194-hsuart";
29 reset-names = "serial";
41 vcc-supply = <&vdd_1v8_sys>;
[all …]

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