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/freebsd/sys/dev/ppbus/
H A Dppb_1284.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
33 * General purpose routines for the IEEE1284-1994 Standard
82 ppb->error = PPB_NO_ERROR; in ppb_1284_reset_error()
83 ppb->state = state; in ppb_1284_reset_error()
98 mtx_assert(ppb->ppc_lock, MA_OWNED); in ppb_1284_get_state()
99 return (ppb->state); in ppb_1284_get_state()
114 mtx_assert(ppb->ppc_lock, MA_OWNED); in ppb_1284_set_state()
115 if ((ppb->state != PPB_ERROR) && in ppb_1284_set_state()
116 (ppb->error == PPB_NO_ERROR)) { in ppb_1284_set_state()
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H A Dlpt.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
35 * ON-LINE 386BSD USER MANUAL BEFORE USE. A BOOK DISCUSSING THE INTERNALS
112 /* default case: negative prime, negative ack, handshake strobe,
165 /* Printer Ready condition - from lpa.c */
172 #define MAX_SPIN 20 /* Max delay for device ready in usecs */
202 if (sc->sc_state & HAVEBUS) in lpt_request_ppbus()
207 sc->sc_state |= HAVEBUS; in lpt_request_ppbus()
219 if (sc->sc_state & HAVEBUS) { in lpt_release_ppbus()
222 sc->sc_state &= ~HAVEBUS; in lpt_release_ppbus()
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dfsl-imx-esdhc.txt7 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
10 - compatible : Should be "fsl,<chip>-esdhc", the supported chips include
11 "fsl,imx25-esdhc"
12 "fsl,imx35-esdhc"
13 "fsl,imx51-esdhc"
14 "fsl,imx53-esdhc"
15 "fsl,imx6q-usdhc"
16 "fsl,imx6sl-usdhc"
17 "fsl,imx6sx-usdhc"
18 "fsl,imx6ull-usdhc"
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H A Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
25 - "axis,artpec8-dw-mshc": for controllers with ARTPEC-8 specific
28 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
32 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
[all …]
H A Dfsl-imx-esdhc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
25 - enum:
26 - fsl,imx25-esdhc
27 - fsl,imx35-esdhc
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H A Dsamsung,exynos-dw-mshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-d
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H A Dsdhci-sprd.txt1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
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H A Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
28 - description: gate clock for enabling/disabling the device
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dti-aemif.txt4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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/freebsd/share/man/man9/
H A Dmicroseq.942 .Bl -enum -offset indent
69 In any other mode, drivers may be tri-stated by
74 This read-only register reflects the inputs on the parallel port interface.
76 .Bl -column "Bit" "Name" "Description" -compact
85 Others are reserved and return undefined result when read.
90 .Bl -column "Bit" "Name " "Description" -compact
97 .It 0 Ta STROBE Ta "inverted and driven as parallel port nStrobe signal"
108 .Bd -literal
114 #define MS_OP_DELAY 5 /* delay <val> */
134 .Bl -bullet -offset indent
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/freebsd/share/misc/
H A Dscsi_modes35 # 'i' is a byte-sized integral types, followed by a field width of
38 # 'b' is a bit-sized integral type
39 # 't' is a bitfield type- followed by a bit field width
42 # 'z' values are null-padded strings
81 {Extended Self-Test Completion Time} i2
95 0x02 "Disconnect-Reconnect" {
111 0x16 "Extended Device-Type Specific";
154 0x18 "Protocol-Specific Logical Unit";
156 0x19 "Protocol-Specific Port";
172 {Background Pre-Scan Time Limit} i2
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/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dcommon.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jacek Anaszewski <jacek.anaszewski@gmail.com>
11 - Pavel Machek <pavel@ucw.cz>
16 blinking patterns, flash timeout, flash faults and external flash strobe mode.
25 led-sources:
30 $ref: /schemas/types.yaml#/definitions/uint32-array
35 from the header include/dt-bindings/leds/common.h. If there is no
42 the header include/dt-bindings/leds/common.h. If there is no matching
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/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroidxu3-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
12 #include <dt-bindings/input/input.h>
13 #include "exynos5422-odroid-core.dtsi"
20 gpio-keys {
21 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&power_key>;
25 power-key {
36 debounce-interval = <0>;
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H A Dexynos5420-smdk5420.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "exynos5420-cpus.dtsi"
12 #include <dt-bindings/clock/samsung,s2mps11.h>
13 #include <dt-bindings/gpio/gpio.h>
31 stdout-path = "serial2:115200n8";
34 fixed-rate-clocks {
36 compatible = "samsung,exynos5420-oscclk";
37 clock-frequency = <24000000>;
41 vdd: regulator-0 {
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H A Dexynos5422-samsung-k3g.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung Galaxy S5 (SM-G900H) device-tree source
8 /dts-v1/;
9 #include <dt-bindings/clock/samsung,s2mps11.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
13 #include "exynos5422-cpus.dtsi"
16 model = "Samsung Galaxy S5 (SM-G900H)";
20 chassis-type = "handset";
31 fixed-rate-clocks {
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H A Dexynos5800-peach-pi.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos5420-cpus.dtsi"
21 compatible = "google,pi-rev16",
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H A Dexynos5420-peach-pit.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
14 #include <dt-bindings/sound/samsung-i2s.h>
16 #include "exynos5420-cpus.dtsi"
21 compatible = "google,pit-rev16",
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/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2004 Atheros Communications, Inc.
24 * Processor for IEEE 802.11a 5-GHz Wireless LANs.
65 #define AR_EP_RDATA 0x6800 /* EEPROM read data register */
72 #define AR_SLOT_TIME 0x8010 /* Length of a back-off */
98 #define AR_BACKOFF 0x8088 /* Back-off status */
127 #define AR_CFG_TXFSTRT 0x00010000 /* re-enable TX DMA */
184 #define AR_IER_DISABLE 0x00000000 /* pseudo-flag */
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3-n900.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
7 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/media/video-interfaces.h>
15 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
17 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
18 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
34 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
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/freebsd/sys/arm64/nvidia/tegra210/
H A Dmax77620_rtc.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
83 #define LOCK(_sc) sx_xlock(&(_sc)->lock)
84 #define UNLOCK(_sc) sx_xunlock(&(_sc)->lock)
85 #define LOCK_INIT(_sc) sx_init(&(_sc)->lock, "max77620_rtc")
86 #define LOCK_DESTROY(_sc) sx_destroy(&(_sc)->lock);
109 msgs[0].slave = sc->bus_addr; in max77620_rtc_read()
110 msgs[1].slave = sc->bus_addr; in max77620_rtc_read()
113 rv = iicbus_transfer(sc->dev, msgs, 2); in max77620_rtc_read()
115 device_printf(sc->dev, in max77620_rtc_read()
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/freebsd/sys/dev/rl/
H A Dif_rl.c1 /*-
16 * 4. Neither the name of the author nor the names of any co-contributors
48 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
50 * gains that bus-master DMA usually offers.
54 * on a longword (32-bit) boundary. This means we almost always have to
57 * is 32-bit aligned within the mbuf's data area. The presence of only
72 * On the bright side, the 8139 does have a built-in PHY, although
75 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * the 8139 lets you directly access the on-board PHY registers. We need
151 "D-Link DFE-520TX (rev. C1) 10/100BaseTX" },
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/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos5433-tm2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 /dts-v1/;
13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-binding
[all...]
/freebsd/sys/dev/sdhci/
H A Dsdhci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off))
82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off))
83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off))
85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val))
88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val))
89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val))
91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
[all …]
/freebsd/sys/dev/dc/
H A Dif_dc.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
41 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com)
42 * Lite-On 82c168/82c169 PNIC (www.litecom.com)
179 "Compex RL100-TX 10/100BaseTX" },
181 "Compex RL100-TX 10/100BaseTX" },
185 "Macronix 98715AEC-C 10/100BaseTX" },
203 "Neteasy DRP-32TXD Cardbus 10/100" },
213 "PlaneX FNW-3602-T CardBus 10/100" },
[all …]
/freebsd/sys/dev/re/
H A Dif_re.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998-2003
18 * 4. Neither the name of the author nor the names of any co-contributors
59 * o 64-bit DMA
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
97 * (the 'S' stands for 'single-chip'). These devices have the same
[all …]

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