Searched +full:r9a09g077 +full:- +full:rsci (Results 1 – 5 of 5) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/serial/renesas,rsci.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas RSCI Serial Communication Interface10 - Geert Uytterhoeven <geert+renesas@glider.be>11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>14 - $ref: serial.yaml#19 - items:20 - const: renesas,r9a09g087-rsci # RZ/N2H[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>13 #address-cells = <2>;14 #size-cells = <2>;15 interrupt-parent = <&gic>;18 #address-cells = <1>;19 #size-cells = <0>;22 compatible = "arm,cortex-a55";25 next-level-cache = <&L3_CA55>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>12 compatible = "renesas,r9a09g077";13 #address-cells = <2>;14 #size-cells = <2>;15 interrupt-parent = <&gic>;18 #address-cells = <1>;19 #size-cells = <0>;22 compatible = "arm,cortex-a55";[all …]
1 // SPDX-License-Identifier: GPL-2.014 #include "rsci.h"18 /* RSCI registers */58 #define CCR1_SHARPS BIT(20) /* Half -duplex Communication Select */90 #define SCxSR_ERRORS(port) (to_sci_port(port)->params->error_mask)91 #define SCxSR_ERROR_CLEAR(port) (to_sci_port(port)->params->error_clear)126 return readl(p->membase + offset); in rsci_serial_in()131 writel(value, p->membase + offset); in rsci_serial_out()164 if (termios->c_cflag & CREAD) in rsci_set_termios()212 if (sp->chan_tx) in rsci_start_tx()[all …]
1 // SPDX-License-Identifier: GPL-2.03 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)5 * Copyright (C) 2002 - 2011 Paul Mundt9 * based off of the old drivers/char/sh-sci.c by:26 #include <linux/dma-mapping.h>60 #include "rsci.h"62 #include "sh-sci-common.h"96 #define SCSMR_CSYNC BIT(7) /* - Clocked synchronous mode */97 #define SCSMR_ASYNC 0 /* - Asynchronous mode */98 #define SCSMR_CHR BIT(6) /* 7-bit Character Length */[all …]