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/linux/Documentation/devicetree/bindings/dma/
H A Drenesas,rz-dmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
15 - items:
16 - enum:
17 - renesas,r7s72100-dmac # RZ/A1H
18 - renesas,r9a07g043-dmac # RZ/G2UL and RZ/Five
19 - renesas,r9a07g044-dmac # RZ/G2{L,LC}
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/linux/drivers/irqchip/
H A Dirq-renesas-rzv2h.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/V2H(P) ICU Driver
5 * Based on irq-renesas-rzg2l.c
17 #include <linux/irqchip/irq-renesas-rzv2h.h>
71 ICU_TSSR_TSSEL_PREP((GENMASK(((_field_width) - 2), 0)), (n), _field_width); \
77 BIT((_field_width) - 1) << ((n) * (_field_width)); \
93 * struct rzv2h_hw_info - Interrupt Control Unit controller hardware info structure.
116 * struct rzv2h_icu_priv - Interrupt Control Unit controller private data structure.
142 guard(raw_spinlock_irqsave)(&priv->lock); in rzv2h_icu_register_dma_req()
144 icu_dmksely = readl(priv->base + ICU_DMkSELy(dmac_index, y)); in rzv2h_icu_register_dma_req()
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/linux/drivers/dma/sh/
H A Drz-dmac.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on imx-dma.c
9 * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
13 #include <linux/dma-mapping.h>
17 #include <linux/irqchip/irq-renesas-rzv2h.h>
30 #include "../virt-dma.h"
100 struct rz_dmac_icu icu; member
117 * -----------------------------------------------------------------------------
179 /* RZ/V2H ICU related */
183 * -----------------------------------------------------------------------------
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/linux/drivers/watchdog/
H A Drzv2h_wdt.c1 // SPDX-License-Identifier: GPL-2.0
83 * The down-counter is refreshed and starts counting operation on in rzv2h_wdt_ping()
86 writeb(0x0, priv->base + WDTRR); in rzv2h_wdt_ping()
87 writeb(0xFF, priv->base + WDTRR); in rzv2h_wdt_ping()
94 u32 reg = readl(priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_stop()
96 writel(reg | WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_stop()
101 u32 reg = readl(priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_start()
103 writel(reg & ~WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR); in rzt2h_wdt_wdtdcr_count_start()
111 writew(wdtcr, priv->base + WDTCR); in rzv2h_wdt_setup()
113 /* Enable interrupt output to the ICU. */ in rzv2h_wdt_setup()
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