Searched +full:r9a07g044 +full:- +full:adc (Results 1 – 6 of 6) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzg2l-adc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas RZ/G2L ADC10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>13 A/D Converter block is a successive approximation analog-to-digital converter14 with a 12-bit accuracy. Up to eight analog input channels can be selected.15 Conversions can be performed in single or repeat mode. Result of the ADC is16 stored in a 32-bit data register corresponding to each channel.[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g044-cpg.h>12 compatible = "renesas,r9a07g044";13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 /dts-v1/;9 #include "r9a07g044.dtsi"12 compatible = "renesas,r9a07g044c2", "renesas,r9a07g044";16 /delete-node/ ssi@1004a800;17 /delete-node/ serial@1004c800;18 /delete-node/ adc@10059000;19 /delete-node/ ethernet@11c30000;
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 /dts-v1/;9 #include "r9a07g044.dtsi"12 compatible = "renesas,r9a07g044c1", "renesas,r9a07g044";15 /delete-node/ cpu-map;16 /delete-node/ cpu@100;21 /delete-node/ ssi@1004a800;22 /delete-node/ serial@1004c800;23 /delete-node/ adc@10059000;24 /delete-node/ ethernet@11c30000;
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/r9a07g054-cpg.h>13 #address-cells = <2>;14 #size-cells = <2>;16 audio_clk1: audio1-clk {17 compatible = "fixed-clock";18 #clock-cells = <0>;20 clock-frequency = <0>;23 audio_clk2: audio2-clk {[all …]
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)8 #include <dt-bindings/clock/r9a07g043-cpg.h>12 #address-cells = <2>;13 #size-cells = <2>;15 audio_clk1: audio1-clk {16 compatible = "fixed-clock";17 #clock-cells = <0>;19 clock-frequency = <0>;22 audio_clk2: audio2-clk {23 compatible = "fixed-clock";[all …]