Home
last modified time | relevance | path

Searched +full:r9a06g032 +full:- +full:adc (Results 1 – 2 of 2) sorted by relevance

/linux/Documentation/devicetree/bindings/iio/adc/
H A Drenesas,rzn1-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rzn1-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 Analog to Digital Converter (ADC)
10 - Herve Codina <herve.codina@bootlin.com>
13 The Renesas RZ/N1 ADC controller available in the Renesas RZ/N1 SoCs family
14 can use up to two internal ADC cores (ADC1 and ADC2) those internal cores are
15 handled through ADC controller virtual channels.
20 - const: renesas,r9a06g032-adc # RZ/N1D
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
13 compatible = "renesas,r9a06g032";
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&gic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]