Searched +full:r8a779f0 +full:- +full:ether +full:- +full:switch (Results 1 – 3 of 3) sorted by relevance
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | renesas,r8a779f0-ether-switch.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/renesas,r8a779f0-ether-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet Switch
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
14 const: renesas,r8a779f0-ether-switch
19 reg-names:
21 - const: base
22 - const: secure_base
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a779f0.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h>
13 compatible = "renesas,r8a779f0";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 cluster01_opp: opp-table-0 {
18 compatible = "operating-points-v2";
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| /linux/drivers/phy/renesas/ |
| H A D | r8a779f0-ether-serdes.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2022-2025 Renesas Electronics Corporation
66 iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT); in r8a779f0_eth_serdes_reg_wait()
68 ret = readl_poll_timeout_atomic(channel->addr + offs, val, in r8a779f0_eth_serdes_reg_wait()
72 dev_dbg(&channel->phy->dev, in r8a779f0_eth_serdes_reg_wait()
74 __func__, channel->index, offs, bank, mask, expected); in r8a779f0_eth_serdes_reg_wait()
86 channel = &dd->channel[i]; in r8a779f0_eth_serdes_common_init_ram()
92 r8a779f0_eth_serdes_write32(dd->addr, 0x026c, 0x180, 0x03); in r8a779f0_eth_serdes_common_init_ram()
100 struct r8a779f0_eth_serdes_drv_data *dd = channel->dd; in r8a779f0_eth_serdes_common_setting()
103 r8a779f0_eth_serdes_write32(dd->addr, 0x0244, 0x180, 0x00d7); in r8a779f0_eth_serdes_common_setting()
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