Searched +full:r8a73a4 +full:- +full:div6 +full:- +full:clock (Results 1 – 2 of 2) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the r8a73a4 SoC9 #include <dt-bindings/clock/r8a73a4-clock.h>10 #include <dt-bindings/interrupt-controller/arm-gic.h>11 #include <dt-bindings/interrupt-controller/irq.h>14 compatible = "renesas,r8a73a4";15 interrupt-parent = <&gic>;16 #address-cells = <2>;17 #size-cells = <2>;20 #address-cells = <1>;[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Renesas CPG DIV6 Clock10 - Geert Uytterhoeven <geert+renesas@glider.be>13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse14 Generator (CPG). Their clock input is divided by a configurable factor from 120 - enum:21 - renesas,r8a73a4-div6-clock # R-Mobile APE6[all …]