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Searched +full:r8a73a4 +full:- +full:cpg +full:- +full:clocks (Results 1 – 11 of 11) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-div6-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas CPG DIV6 Clock
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14 Generator (CPG). Their clock input is divided by a configurable factor from 1
20 - enum:
21 - renesas,r8a73a4-div6-clock # R-Mobile APE6
[all …]
H A Drenesas,cpg-mstp-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
16 This device tree binding describes a single 32 gate clocks group per node.
17 Clocks are referenced by user nodes by the Module Stop (MSTP) node phandle
23 - enum:
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H A Drenesas,cpg-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Drcar-thermal.yaml1 # SPDX-License-Identifier: GPL-2.0-only
4 ---
5 $id: http://devicetree.org/schemas/thermal/rcar-thermal.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Thermal
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
16 - items:
17 - enum:
18 - renesas,thermal-r8a73a4 # R-Mobile APE6
19 - renesas,thermal-r8a7779 # R-Car H1
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/linux/Documentation/devicetree/bindings/mmc/
H A Drenesas,mmcif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
13 - $ref: mmc-controller.yaml
18 - enum:
19 - renesas,mmcif-r7s72100 # RZ/A1H
20 - renesas,mmcif-r8a73a4 # R-Mobile APE6
21 - renesas,mmcif-r8a7740 # R-Mobile A1
22 - renesas,mmcif-r8a7742 # RZ/G1H
[all …]
H A Drenesas,sdhi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
15 - enum:
16 - renesas,sdhi-mmc-r8a77470 # RZ/G1C
17 - renesas,sdhi-r7s72100 # RZ/A1H
18 - renesas,sdhi-r7s9210 # SH-Mobile AG5
19 - renesas,sdhi-r8a73a4 # R-Mobile APE6
20 - renesas,sdhi-r8a7740 # R-Mobile A1
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/linux/drivers/clk/renesas/
H A Dclk-r8a73a4.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a73a4 Core CPG Clocks
8 #include <linux/clk-provider.h>
58 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, in r8a73a4_cpg_register_clock() argument
87 /* PLL0/1 are configurable multiplier clocks. Register them as in r8a73a4_cpg_register_clock()
88 * fixed factor clocks for now as there's no generic multiplier in r8a73a4_cpg_register_clock()
120 return ERR_PTR(-EINVAL); in r8a73a4_cpg_register_clock()
145 return ERR_PTR(-EINVAL); in r8a73a4_cpg_register_clock()
158 mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f); in r8a73a4_cpg_register_clock()
162 for (c = div4_clks; c->name; c++) { in r8a73a4_cpg_register_clock()
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H A Dclk-mstp.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car MSTP clocks
12 #include <linux/clk-provider.h>
25 * MSTP clocks. We can't use standard gate clocks as we need to poll on the
32 * struct mstp_clock_group - MSTP gating clocks group
34 * @data: clock specifier translation for clocks in this group
38 * @width_8bit: registers are 8-bit, not 32-bit
39 * @clks: clocks in this group
51 * struct mstp_clock - MSTP gating clock
52 * @hw: handle between common and hardware-specific interfaces
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/linux/Documentation/devicetree/bindings/serial/
H A Drenesas,scifa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 - $ref: serial.yaml#
18 - items:
19 - enum:
20 - renesas,scifa-r8a73a4 # R-Mobile APE6
21 - renesas,scifa-r8a7740 # R-Mobile A1
22 - renesas,scifa-sh73a0 # SH-Mobile AG5
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Drenesas,irqc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: R-Mobile/R-Car/RZ/G interrupt controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
15 - enum:
16 - renesas,irqc-r8a73a4 # R-Mobile APE6
17 - renesas,irqc-r8a7742 # RZ/G1H
18 - renesas,irqc-r8a7743 # RZ/G1M
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Drenesas,rmobile-iic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/renesas,rmobile-iic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Mobile I2C Bus Interface (IIC)
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
15 - items:
16 - enum:
17 - renesas,iic-r8a73a4 # R-Mobile APE6
18 - renesas,iic-r8a7740 # R-Mobile A1
[all …]