xref: /freebsd/sys/contrib/device-tree/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SA8775P TLMM block
8
9maintainers:
10  - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
11
12description: |
13  Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sa8775p-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  gpio-reserved-ranges:
29    minItems: 1
30    maxItems: 74
31
32  gpio-line-names:
33    maxItems: 148
34
35patternProperties:
36  "-state$":
37    oneOf:
38      - $ref: "#/$defs/qcom-sa8775p-tlmm-state"
39      - patternProperties:
40          "-pins$":
41            $ref: "#/$defs/qcom-sa8775p-tlmm-state"
42        additionalProperties: false
43
44$defs:
45  qcom-sa8775p-tlmm-state:
46    type: object
47    description:
48      Pinctrl node's client devices use subnodes for desired pin configuration.
49      Client device subnodes use below standard properties.
50    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
51    unevaluatedProperties: false
52
53    properties:
54      pins:
55        description:
56          List of gpio pins affected by the properties specified in this
57          subnode.
58        items:
59          oneOf:
60            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$"
61            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ]
62        minItems: 1
63        maxItems: 16
64
65      function:
66        description:
67          Specify the alternative function to be configured for the specified
68          pins.
69
70        enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c,
71                cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
72                cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
73                cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
74                ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot,
75                edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot,
76                edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3,
77                emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0,
78                emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio,
79                emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3,
80                gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
81                jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3,
82                mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8,
83                mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
84                mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
85                mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0,
86                mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1,
87                pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk,
88                prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
89                qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
90                qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
91                qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3,
92                qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0,
93                sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1,
94                tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2,
95                tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ]
96
97    required:
98      - pins
99
100required:
101  - compatible
102  - reg
103
104unevaluatedProperties: false
105
106examples:
107  - |
108    #include <dt-bindings/interrupt-controller/arm-gic.h>
109
110    tlmm: pinctrl@f000000 {
111        compatible = "qcom,sa8775p-tlmm";
112        reg = <0xf000000 0x1000000>;
113        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
114        gpio-controller;
115        #gpio-cells = <2>;
116        interrupt-controller;
117        #interrupt-cells = <2>;
118        gpio-ranges = <&tlmm 0 0 148>;
119
120        qup-uart10-state {
121            pins = "gpio46", "gpio47";
122            function = "qup1_se3";
123        };
124    };
125...
126