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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti,phy-gmii-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
20 +--------------+
21 +-------------------------------+ |SCM |
22 | CPSW | | +---------+ |
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/freebsd/sys/contrib/ncsw/Peripherals/FM/MAC/
H A Dmemac.c2 * Copyright 2008-2012 Freescale Semiconductor Inc.
75 xorVal |= (mask1 << (5-i)); in GetMacAddrHashCode()
89 speed=10000 is provided for SGMII ports. Temporary modify enet mode in SetupSgmiiInternalPhy()
91 enetMode = p_Memac->enetMode; in SetupSgmiiInternalPhy()
95 if ((p_Memac->enetMode) == e_ENET_MODE_SGMII_2500) in SetupSgmiiInternalPhy()
98 …p_Memac->enetMode = MAKE_ENET_MODE(ENET_INTERFACE_FROM_MODE(p_Memac->enetMode), e_ENET_SPEED_1000); in SetupSgmiiInternalPhy()
105 /* Adjust link timer for SGMII - in SetupSgmiiInternalPhy()
108 - When running as 1G SGMII, Serdes clock is 125 MHz, so in SetupSgmiiInternalPhy()
111 - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so in SetupSgmiiInternalPhy()
124 p_Memac->enetMode = enetMode; in SetupSgmiiInternalPhy()
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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j784s4-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals
5 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-ti.h>
12 #include "k3-serdes.h"
15 serdes_refclk: clock-serdes {
16 #clock-cells = <0>;
17 compatible = "fixed-clock";
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H A Dk3-j7200-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Device Tree Source for J7200 SoC Family Main Domain peripherals
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
9 serdes_refclk: serdes-refclk {
10 #clock-cells = <0>;
11 compatible = "fixed-clock";
17 compatible = "mmio-sram";
19 #address-cells = <1>;
20 #size-cells = <1>;
23 atf-sram@0 {
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H A Dk3-j721e-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/phy/phy-ti.h>
9 #include <dt-bindings/mux/mux.h>
11 #include "k3-serdes.h"
14 cmn_refclk: clock-cmnrefclk {
15 #clock-cells = <0>;
16 compatible = "fixed-clock";
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