Home
last modified time | relevance | path

Searched +full:qoriq +full:- +full:rcpm +full:- +full:2 (Results 1 – 25 of 26) sorted by relevance

12

/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/
H A Drcpm.txt2 -------------------------------------------
3 The RCPM performs all device-level tasks associated with device run control
7 - reg : Offset and length of the register set of the RCPM block.
8 - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the
9 fsl,rcpm-wakeup property.
10 - compatible : Must contain a chip-specific RCPM block compatible string
11 and (if applicable) may contain a chassis-version RCPM compatible
12 string. Chip-specific strings are of the form "fsl,<chip>-rcpm",
14 * "fsl,p2041-rcpm"
15 * "fsl,p5020-rcpm"
[all …]
H A Dfsl,rcpm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/fsl,rcpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The RCPM performs all device-level tasks associated with device run control
14 - Frank Li <Frank.Li@nxp.com>
19 - items:
20 - enum:
21 - fsl,p2041-rcpm
22 - fsl,p3041-rcpm
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Db4420si-post.dtsi20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
43 dcsr-epu@0 {
44 compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
46 dcsr-npc {
47 compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
49 dcsr-dpaa@9000 {
50 compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
52 dcsr-ocn@11000 {
[all …]
H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
52 interrupts = <25 2 0 0>;
[all …]
H A Db4860si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
44 interrupts = <16 2 1 20>;
45 #address-cells = <2>;
46 #size-cells = <2>;
47 fsl,iommu-parent = <&pamu0>;
51 #address-cells = <2>;
52 #size-cells = <2>;
[all …]
H A Dt1023si-post.dtsi20 * Foundation, either version 2 of that License or (at your option) any
35 #include <dt-bindings/thermal/thermal.h>
38 compatible = "fsl,bman-fbpr";
39 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,qman-fqd";
44 alloc-ranges = <0 0 0x10000 0>;
48 compatible = "fsl,qman-pfdr";
49 alloc-ranges = <0 0 0x10000 0>;
53 #address-cells = <2>;
54 #size-cells = <1>;
[all …]
H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
52 interrupts = <25 2 0 0>;
[all …]
H A Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
52 interrupts = <25 2 0 0>;
[all …]
H A Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
52 interrupts = <25 2 0 0>;
[all …]
H A Db4si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor, Inc.
20 * Foundation, either version 2 of that License or (at your option) any
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
[all …]
H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
52 interrupts = <25 2 0 0>;
[all …]
H A Dt2081si-post.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
[all …]
H A Dt1040si-post.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 #include <dt-bindings/thermal/thermal.h>
38 compatible = "fsl,bman-fbpr";
39 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,qman-fqd";
44 alloc-ranges = <0 0 0x10000 0>;
48 compatible = "fsl,qman-pfdr";
49 alloc-ranges = <0 0 0x10000 0>;
53 #address-cells = <2>;
[all …]
H A Dt4240si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1088a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
[all …]
H A Dfsl-ls208xa.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
[all …]
H A Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
[all …]
H A Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
H A Dfsl-lx2160a.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/ls/
H A Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
[all …]
/freebsd/sys/dts/powerpc/
H A Dp3041si.dtsi4 * Copyright 2010-2011 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
102 #address-cells = <1>;
103 #size-cells = <0>;
108 bus-frequency = <749999996>;
109 next-level-cache = <&L2_0>;
[all …]
H A Dp2041si.dtsi20 * Foundation, either version 2 of that License or (at your option) any
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
101 #address-cells = <1>;
102 #size-cells = <0>;
107 bus-frequency = <749999996>;
108 next-level-cache = <&L2_0>;
109 L2_0: l2-cache {
[all …]
H A Dp5020si.dtsi4 * Copyright 2010-2011 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /dts-v1/;
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
108 #address-cells = <1>;
109 #size-cells = <0>;
114 bus-frequency = <799999998>;
115 next-level-cache = <&L2_0>;
[all …]

12