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Searched +full:qman +full:- +full:channel +full:- +full:range (Results 1 – 14 of 14) sorted by relevance

/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
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/linux/drivers/soc/fsl/qbman/
H A Dqman_ccsr.c1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
101 * Corenet initiator settings. Stash request queues are 4-deep to match cores
111 /* Follows WQ_CS_CFG0-5 */
134 #define QM_EIRQ_MBEI 0x02000000 /* Multi-bit ECC Error */
135 #define QM_EIRQ_SBEI 0x01000000 /* Single-bit ECC Error */
139 #define QM_EIRQ_IDDI 0x00000800 /* Invalid Dequeue (Direct-connect) */
146 #define QM_EIRQ_IECI 0x00000002 /* Invalid Enqueue Channel */
158 u32 info; /* res[30-31], ptyp[29], pnum[24-28], fqid[0-23] */
163 return p->info & BIT(29); in qm_ecir_is_dcp()
168 return (p->info >> 24) & 0x1f; in qm_ecir_get_pnum()
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H A Dqman.c1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
35 #define IRQNAME "QMan portal %d"
36 #define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
47 /* Cache-inhibited register offsets */
68 /* Cache-enabled register offsets */
83 /* Cache-inhibited register offsets */
104 /* Cache-enabled register offsets */
121 * synchronisation for portal accesses and data-dependencies. Use of barrier()s
122 * or other order-preserving primitives simply degrade performance. Hence the
127 /* Cache-enabled ring access */
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/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright 2012-2015 Freescale Semiconductor Inc.
9 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
14 cell-index = <0>;
21 clock-names = "fmanclk";
22 fsl,qman-channel-range = <0x800 0x10>;
23 ptimer-handle = <&ptp_timer0>;
24 dma-coherent;
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/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-1.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x820 0x10>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x2>;
55 compatible = "fsl,fman-v3-port-oh";
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H A Dqoriq-fman-1.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <1>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x60 0xc>;
46 ptimer-handle = <&ptp_timer1>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x1>;
55 compatible = "fsl,fman-v2-port-oh";
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H A Dqoriq-fman3l-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x800 0x10>;
46 ptimer-handle = <&ptp_timer0>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x2>;
55 compatible = "fsl,fman-v3-port-oh";
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H A Dqoriq-fman-0.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x40 0xc>;
46 ptimer-handle = <&ptp_timer0>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x1>;
55 compatible = "fsl,fman-v2-port-oh";
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H A Dqoriq-fman3-0.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 #address-cells = <1>;
37 #size-cells = <1>;
38 cell-index = <0>;
44 clock-names = "fmanclk";
45 fsl,qman-channel-range = <0x800 0x10>;
46 ptimer-handle = <&ptp_timer0>;
49 compatible = "fsl,fman-muram";
54 cell-index = <0x2>;
55 compatible = "fsl,fman-v3-port-oh";
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/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24 * - MMU
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
31 * - Range registers
32 * - Protection bits
36 * QMAN DMA: PQ, CQ, CP, DMA are secured.
39 * QMAN TPC/MME:
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/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
27 * - Range registers
28 * - MMU
31 * - Range registers (protect the first 512MB)
34 * - Range registers
35 * - Protection bits
39 * QMAN DMA channels 0,1 (PCI DMAN):
40 * - DMA is not secured.
41 * - PQ and CQ are secured.
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/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
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/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2020-2022 HabanaLabs, Ltd.
45 * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs
126 #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)
127 #define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)
131 #define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \
134 #define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
164 /* HW scrambles only bits 0-25 */
732 "qman sei intr",
2114 * and read global errors. Most HW blocks are addressable and those who aren't (N/A)-
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