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/linux/Documentation/devicetree/bindings/soc/fsl/
H A Dfsl,qman-portal.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/fsl,qman-portal.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Portals are memory mapped interfaces to QMan that allow low-latency, lock-less
15 interfaces with the QMan
20 - const: fsl,qman-portal
21 - items:
22 - enum:
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/linux/drivers/soc/fsl/qbman/
H A Dqman_ccsr.c1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
101 * Corenet initiator settings. Stash request queues are 4-deep to match cores
111 /* Follows WQ_CS_CFG0-5 */
134 #define QM_EIRQ_MBEI 0x02000000 /* Multi-bit ECC Error */
135 #define QM_EIRQ_SBEI 0x01000000 /* Single-bit ECC Error */
139 #define QM_EIRQ_IDDI 0x00000800 /* Invalid Dequeue (Direct-connect) */
146 #define QM_EIRQ_IECI 0x00000002 /* Invalid Enqueue Channel */
158 u32 info; /* res[30-31], ptyp[29], pnum[24-28], fqid[0-23] */
163 return p->info & BIT(29); in qm_ecir_is_dcp()
168 return (p->info >> 24) & 0x1f; in qm_ecir_get_pnum()
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H A Dqman_priv.h1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
33 #include <soc/fsl/qman.h>
34 #include <linux/dma-mapping.h>
44 u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */
51 return wq->channel_wq >> 3; in qm_mcr_querywq_get_chan()
74 u8 i_bcnt_hi; /* high 8-bits of 40-bit "Instant" */
75 __be32 i_bcnt_lo; /* low 32-bits of 40-bit */
77 u8 a_bcnt_hi; /* high 8-bits of 40-bit "Average" */
78 __be32 a_bcnt_lo; /* low 32-bits of 40-bit */
84 return ((u64)q->i_bcnt_hi << 32) | be32_to_cpu(q->i_bcnt_lo); in qm_mcr_querycgr_i_get64()
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H A Dqman.c1 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
35 #define IRQNAME "QMan portal %d"
36 #define MAX_IRQNAME 16 /* big enough for "QMan portal %d" */
47 /* Cache-inhibited register offsets */
68 /* Cache-enabled register offsets */
83 /* Cache-inhibited register offsets */
104 /* Cache-enabled register offsets */
121 * synchronisation for portal accesses and data-dependencies. Use of barrier()s
122 * or other order-preserving primitives simply degrade performance. Hence the
127 /* Cache-enabled ring access */
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/linux/Documentation/devicetree/bindings/net/
H A Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/fsl,fman.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
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/linux/include/soc/fsl/
H A Ddpaa2-io.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * Copyright 2014-2016 Freescale Semiconductor Inc.
4 * Copyright 2017-2019 NXP
14 #include "dpaa2-fd.h"
15 #include "dpaa2-global.h"
32 #define DPAA2_IO_ANY_CPU -1
35 * struct dpaa2_io_desc - The DPIO descriptor
36 * @receives_notifications: Use notificaton mode. Non-zero if the DPIO
37 * has a channel.
38 * @has_8prio: Set to non-zero for channel with 8 priority WQs. Ignored
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/linux/Documentation/networking/device_drivers/ethernet/freescale/
H A Ddpaa.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Madalin Bucur <madalin.bucur@nxp.com>
9 - Camelia Groza <camelia.groza@nxp.com>
13 - DPAA Ethernet Overview
14 - DPAA Ethernet Supported SoCs
15 - Configuring DPAA Ethernet in your kernel
16 - DPAA Ethernet Frame Processing
17 - DPAA Ethernet Features
18 - DPAA IRQ Affinity and Receive Side Scaling
19 - Debugging
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/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_port.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
23 /* Queue ID */
193 u32 fmbm_rfqid; /* Rx Frame Queue ID */
194 u32 fmbm_refqid; /* Rx Error Frame Queue ID */
198 u32 reserved0074[0x2]; /* (0x074-0x07C) */
202 /* Buffer Manager pool Information- */
203 u32 fmbm_acnt[FMAN_PORT_MAX_EXT_POOLS_NUM]; /* Allocate Counter- */
204 u32 reserved0130[8]; /* 0x130/0x140 - 0x15F reserved - */
243 u32 fmbm_tcfqid; /* Tx Confirmation Frame Queue ID. */
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/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
23 * - Range registers (When MMU is enabled, DMA RR does NOT protect host)
24 * - MMU
27 * - Range registers (protect the first 512MB)
28 * - MMU (isolation between users)
31 * - Range registers
32 * - Protection bits
36 * QMAN DMA: PQ, CQ, CP, DMA are secured.
39 * QMAN TPC/MME:
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/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
27 * - Range registers
28 * - MMU
31 * - Range registers (protect the first 512MB)
34 * - Range registers
35 * - Protection bits
39 * QMAN DMA channels 0,1 (PCI DMAN):
40 * - DMA is not secured.
41 * - PQ and CQ are secured.
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/linux/drivers/soc/fsl/dpio/
H A Dqbman-portal.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
4 * Copyright 2016-2019 NXP
12 #include <soc/fsl/dpaa2-global.h>
14 #include "qbman-portal.h"
54 /* CENA register offsets in memory-backed mode */
178 return readl_relaxed(p->addr_cinh + offset); in qbman_read_register()
184 writel_relaxed(value, p->addr_cinh + offset); in qbman_write_register()
189 return p->addr_cena + offset; in qbman_get_cmd()
234 return last - first; in qm_cyc_diff()
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/linux/drivers/net/ethernet/freescale/dpaa2/
H A Ddpaa2-eth.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
3 * Copyright 2016-2022 NXP
23 #include "dpaa2-eth.h"
29 #include "dpaa2-eth-trace.h"
40 priv->features = 0; in dpaa2_eth_detect_features()
44 priv->features |= DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT; in dpaa2_eth_detect_features()
57 if (dpni_set_single_step_cfg(priv->mc_io, 0, priv->mc_token, &cfg)) in dpaa2_update_ptp_onestep_indirect()
72 if (priv->onestep_reg_base) in dpaa2_update_ptp_onestep_direct()
73 writel(val, priv->onestep_reg_base); in dpaa2_update_ptp_onestep_direct()
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/linux/drivers/accel/habanalabs/common/
H A Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
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/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2020-2022 HabanaLabs, Ltd.
45 * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs
126 #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0)
127 #define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0)
131 #define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \
134 #define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
164 /* HW scrambles only bits 0-25 */
732 "qman sei intr",
959 {"calculated SO value overflow/underflow", "SOB ID"},
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