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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/cpm_qe/
H A Dfsl,qe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine module (QE)
10 - Frank Li <Frank.Li@nxp.com>
13 This represents qe module that is installed on PowerQUICC II Pro.
20 the "root" qe node, using the common properties from there.
21 The description below applies to the qe of MPC8360 and
27 - const: fsl,qe
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H A Dqe.txt1 * Freescale QUICC Engine module (QE)
2 This represents qe module that is installed on PowerQUICC II Pro.
9 the "root" qe node, using the common properties from there.
10 The description below applies to the qe of MPC8360 and
13 i) Root QE device
16 - compatible : should be "fsl,qe";
17 - model : precise model of the QE, Can be "QE", "CPM", or "CPM2"
18 - reg : offset and length of the device registers.
19 - bus-frequency : the clock frequency for QUICC Engine.
20 - fsl,qe-num-riscs: define how many RISC engines the QE has.
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt1024si-post.dtsi35 #include "t1023si-post.dtsi"
43 qe:qe@ffe140000 { label
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "qe";
47 compatible = "fsl,qe";
50 fsl,qe-num-riscs = <1>;
51 fsl,qe-num-snums = <28>;
52 brg-frequency = <0>;
53 bus-frequency = <0>;
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H A Dp1021si-post.dtsi4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
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H A Dmpc8569si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
56 #interrupt-cells = <1>;
57 #size-cells = <2>;
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H A Dmpc8568si-post.dtsi36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
45 compatible = "fsl,mpc8540-pci";
48 bus-range = <0 0xff>;
49 #interrupt-cells = <1>;
50 #size-cells = <2>;
51 #address-cells = <3>;
57 compatible = "fsl,mpc8548-pcie";
59 #size-cells = <2>;
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H A Dt1040si-post.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
35 #include <dt-bindings/thermal/thermal.h>
38 compatible = "fsl,bman-fbpr";
39 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,qman-fqd";
44 alloc-ranges = <0 0 0x10000 0>;
48 compatible = "fsl,qman-pfdr";
49 alloc-ranges = <0 0 0x10000 0>;
53 #address-cells = <2>;
54 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc836x_rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
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H A Dmpc832x_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <16384>; // L1, 16K
34 i-cache-size = <16384>; // L1, 16K
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H A Dmpc836x_mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
13 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
30 #address-cells = <1>;
31 #size-cells = <0>;
36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <32768>; // L1, 32K
39 i-cache-size = <32768>; // L1, 32K
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H A Dmpc832x_mds.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
12 * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
14 * 3) Solder a wire from U61-22 to P19K-22.
18 * you're going by the schematic, the pin is called "P19J-K22".
21 /dts-v1/;
26 #address-cells = <1>;
27 #size-cells = <1>;
38 #address-cells = <1>;
39 #size-cells = <0>;
44 d-cache-line-size = <32>; // 32 bytes
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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