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Searched +full:qcm2290 +full:- +full:mdss (Results 1 – 10 of 10) sorted by relevance

/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,qcm2290-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QCM220 Display MDSS
10 - Loic Poulain <loic.poulain@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
15 are mentioned for QCM2290 target.
17 $ref: /schemas/display/msm/mdss-common.yaml#
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H A Dqcom,qcm2290-dpu.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU on QCM2290
10 - Loic Poulain <loic.poulain@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,qcm2290-dpu
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
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H A Dqcom,sm6115-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6115-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM6115 Display MDSS
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sm6115-mdss
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H A Ddsi-controller-main.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
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/linux/arch/arm64/boot/dts/qcom/
H A Dqcm2290.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9 #include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10 #include <dt-bindings/clock/qcom,qcm2290-gpucc.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/firmware/qcom,scm.h>
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interconnect/qcom,qcm2290.h>
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H A Dqrb2210-rb1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include <dt-bindings/leds/common.h>
9 #include "qcm2290.dtsi"
14 compatible = "qcom,qrb2210-rb1", "qcom,qrb2210", "qcom,qcm2290";
23 stdout-path = "serial0:115200n8";
27 clk40M: can-clk {
28 compatible = "fixed-clock";
29 clock-frequency = <40000000>;
30 #clock-cells = <0>;
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/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
14 #include "arm-smmu.h"
15 #include "arm-smmu-qcom.h"
17 #define QCOM_DUMMY_VAL -1
32 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in qcom_smmu_tlb_sync()
55 if (qsmmu->stall_enabled & BIT(idx)) in qcom_adreno_smmu_write_sctlr()
65 struct arm_smmu_cfg *cfg = &smmu_domain->cfg; in qcom_adreno_smmu_get_fault_info()
66 struct arm_smmu_device *smmu = smmu_domain->smmu; in qcom_adreno_smmu_get_fault_info()
68 info->fsr = arm_smmu_cb_read(smmu, cfg->cbndx, ARM_SMMU_CB_FSR); in qcom_adreno_smmu_get_fault_info()
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/linux/drivers/gpu/drm/msm/
H A Dmsm_mdss.c2 * SPDX-License-Identifier: GPL-2.0
32 #define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */
58 path0 = devm_of_icc_get(dev, "mdp0-mem"); in msm_mdss_parse_data_bus_icc_path()
62 msm_mdss->mdp_path[0] = path0; in msm_mdss_parse_data_bus_icc_path()
63 msm_mdss->num_mdp_paths = 1; in msm_mdss_parse_data_bus_icc_path()
65 path1 = devm_of_icc_get(dev, "mdp1-mem"); in msm_mdss_parse_data_bus_icc_path()
67 msm_mdss->mdp_path[1] = path1; in msm_mdss_parse_data_bus_icc_path()
68 msm_mdss->num_mdp_paths++; in msm_mdss_parse_data_bus_icc_path()
71 reg_bus_path = of_icc_get(dev, "cpu-cfg"); in msm_mdss_parse_data_bus_icc_path()
73 msm_mdss->reg_bus_path = reg_bus_path; in msm_mdss_parse_data_bus_icc_path()
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/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
10 unsigned long host_flags = msm_dsi_host_get_mode_flags(msm_dsi->host); in msm_dsi_is_cmd_mode()
17 return msm_dsi_host_get_dsc_config(msm_dsi->host); in msm_dsi_get_dsc_config()
22 return msm_dsi_host_is_wide_bus_enabled(msm_dsi->host); in msm_dsi_wide_bus_enabled()
27 struct platform_device *pdev = msm_dsi->pdev; in dsi_get_phy()
31 phy_node = of_parse_phandle(pdev->dev.of_node, "phys", 0); in dsi_get_phy()
33 DRM_DEV_ERROR(&pdev->dev, "cannot find phy device\n"); in dsi_get_phy()
34 return -ENXIO; in dsi_get_phy()
39 msm_dsi->phy = platform_get_drvdata(phy_pdev); in dsi_get_phy()
40 msm_dsi->phy_dev = &phy_pdev->dev; in dsi_get_phy()
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_kms.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
13 #include <linux/dma-buf.h>
62 struct dpu_kms *kms = s->private; in _dpu_danger_signal_status()
65 if (!kms->hw_mdp) { in _dpu_danger_signal_status()
72 pm_runtime_get_sync(&kms->pdev->dev); in _dpu_danger_signal_status()
75 if (kms->hw_mdp->ops.get_danger_status) in _dpu_danger_signal_status()
76 kms->hw_mdp->ops.get_danger_status(kms->hw_mdp, in _dpu_danger_signal_status()
80 if (kms->hw_mdp->ops.get_safe_status) in _dpu_danger_signal_status()
81 kms->hw_mdp->ops.get_safe_status(kms->hw_mdp, in _dpu_danger_signal_status()
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