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Searched full:pxclk (Results 1 – 7 of 7) sorted by relevance

/linux/arch/powerpc/platforms/85xx/
H A Dp1022_rdk.c49 u32 pxclk; in p1022rdk_set_pixel_clock() local
71 * 'pxclk' is the ratio of the platform clock to the pixel clock. in p1022rdk_set_pixel_clock()
75 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); in p1022rdk_set_pixel_clock()
76 pxclk = clamp_t(u32, pxclk, 2, 255); in p1022rdk_set_pixel_clock()
82 /* Enable the clock and set the pxclk */ in p1022rdk_set_pixel_clock()
83 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); in p1022rdk_set_pixel_clock()
H A Dt1042rdb_diu.c82 u32 pxclk; in t1042rdb_set_pixel_clock() local
105 * 'pxclk' is the ratio of the platform clock to the pixel clock. in t1042rdb_set_pixel_clock()
109 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); in t1042rdb_set_pixel_clock()
110 pxclk = clamp_t(u32, pxclk, 2, 255); in t1042rdb_set_pixel_clock()
116 /* Enable the clock and set the pxclk */ in t1042rdb_set_pixel_clock()
117 setbits32(scfg + CCSR_SCFG_PIXCLKCR, PIXCLKCR_PXCKEN | (pxclk << 16)); in t1042rdb_set_pixel_clock()
H A Dp1022_ds.c379 u32 pxclk; in p1022ds_set_pixel_clock() local
401 * 'pxclk' is the ratio of the platform clock to the pixel clock. in p1022ds_set_pixel_clock()
405 pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq); in p1022ds_set_pixel_clock()
406 pxclk = clamp_t(u32, pxclk, 2, 255); in p1022ds_set_pixel_clock()
412 /* Enable the clock and set the pxclk */ in p1022ds_set_pixel_clock()
413 setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16)); in p1022ds_set_pixel_clock()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_bios.h171 int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
174 int head, int pxclk);
176 enum LVDS_script, int pxclk);
/linux/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_dev.c113 clk = of_clk_get_by_name(np, "pxclk"); in komeda_parse_pipe_dt()
115 DRM_ERROR("get pxclk for pipeline %d failed!\n", pipe->id); in komeda_parse_pipe_dt()
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.h146 * 0x08 or 0x09 pxclk in MHz
H A Ddfp.c544 /* pxclk of 0 is fine for PANEL_OFF, and for a in nv04_lvds_dpms()