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/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-amlogic.yaml4 $id: http://devicetree.org/schemas/pwm/pwm-amlogic.yaml#
7 title: Amlogic PWM
16 - amlogic,meson8b-pwm
17 - amlogic,meson-gxbb-pwm
18 - amlogic,meson-gxbb-ao-pwm
19 - amlogic,meson-axg-ee-pwm
20 - amlogic,meson-axg-ao-pwm
21 - amlogic,meson-g12a-ee-pwm
22 - amlogic,meson-g12a-ao-pwm-ab
23 - amlogic,meson-g12a-ao-pwm-cd
[all …]
H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
18 An optional property "pwm-names" may contain a list of strings to label
[all …]
H A Drenesas,pwm-rcar.yaml4 $id: http://devicetree.org/schemas/pwm/renesas,pwm-rcar.yaml#
7 title: Renesas R-Car PWM Timer Controller
16 - renesas,pwm-r8a7742 # RZ/G1H
17 - renesas,pwm-r8a7743 # RZ/G1M
18 - renesas,pwm-r8a7744 # RZ/G1N
19 - renesas,pwm-r8a7745 # RZ/G1E
20 - renesas,pwm-r8a77470 # RZ/G1C
21 - renesas,pwm-r8a774a1 # RZ/G2M
22 - renesas,pwm-r8a774b1 # RZ/G2N
23 - renesas,pwm-r8a774c0 # RZ/G2E
[all …]
H A Dpwm-samsung.yaml4 $id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
7 title: Samsung SoC PWM timers
14 Samsung SoCs contain PWM timer blocks which can be used for system clock source
15 and clock event timers, as well as to drive SoC outputs with PWM signal. Each
16 PWM timer block provides 5 PWM channels (not all of them can drive physical
25 - samsung,s3c2410-pwm # 16-bit, S3C24xx
26 - samsung,s3c6400-pwm # 32-bit, S3C64xx
27 - samsung,s5p6440-pwm # 3
[all...]
H A Dimx-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
7 title: Freescale i.MX PWM controller
13 - $ref: pwm.yaml#
16 "#pwm-cells":
19 PWM_POLARITY_INVERTED. fsl,imx1-pwm does not support this flags.
25 - fsl,imx1-pwm
26 - fsl,imx27-pwm
29 - fsl,imx25-pwm
30 - fsl,imx31-pwm
31 - fsl,imx50-pwm
[all …]
H A Dpwm-rockchip.yaml4 $id: http://devicetree.org/schemas/pwm/pwm-rockchip.yaml#
7 title: Rockchip PWM controller
15 - const: rockchip,rk2928-pwm
16 - const: rockchip,rk3288-pwm
17 - const: rockchip,rk3328-pwm
18 - const: rockchip,vop-pwm
20 - const: rockchip,rk3036-pwm
21 - const: rockchip,rk2928-pwm
24 - rockchip,rk3128-pwm
[all...]
H A Dallwinner,sun4i-a10-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/allwinner,sun4i-a10-pwm.yaml#
7 title: Allwinner A10 PWM
14 "#pwm-cells":
19 - const: allwinner,sun4i-a10-pwm
20 - const: allwinner,sun5i-a10s-pwm
21 - const: allwinner,sun5i-a13-pwm
22 - const: allwinner,sun7i-a20-pwm
23 - const: allwinner,sun8i-h3-pwm
25 - const: allwinner,sun8i-a83t-pwm
26 - const: allwinner,sun8i-h3-pwm
[all …]
H A Dpwm-mediatek.txt1 MediaTek PWM controller
4 - compatible: should be "mediatek,<name>-pwm":
5 - "mediatek,mt2712-pwm": found on mt2712 SoC.
6 - "mediatek,mt6795-pwm": found on mt6795 SoC.
7 - "mediatek,mt7622-pwm": found on mt7622 SoC.
8 - "mediatek,mt7623-pwm": found on mt7623 SoC.
9 - "mediatek,mt7628-pwm": found on mt7628 SoC.
10 - "mediatek,mt7629-pwm": found on mt7629 SoC.
11 - "mediatek,mt8183-pwm": found on mt8183 SoC.
12 - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
[all …]
H A Dnvidia,tegra20-pwm.txt5 - "nvidia,tegra20-pwm": for Tegra20
6 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
7 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
8 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
9 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
10 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
11 - "nvidia,tegra186-pwm": for Tegra186
12 - "nvidia,tegra194-pwm": for Tegra194
14 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
21 - pwm
[all …]
H A Dpwm-sifive.yaml5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
18 achievable period. PWM RTL that corresponds to the IP block version
21 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
24 - $ref: pwm.yaml#
30 - sifive,fu540-c000-pwm
31 - sifive,fu740-c000-pwm
34 Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
[all …]
H A Dnvidia,tegra20-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/nvidia,tegra20-pwm.yaml#
17 - nvidia,tegra20-pwm
18 - nvidia,tegra186-pwm
22 - nvidia,tegra30-pwm
23 - nvidia,tegra114-pwm
24 - nvidia,tegra124-pwm
25 - nvidia,tegra132-pwm
26 - nvidia,tegra210-pwm
28 - nvidia,tegra20-pwm
31 - const: nvidia,tegra194-pwm
[all …]
H A Dmediatek,mt2712-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
7 title: MediaTek PWM Controller
13 - $ref: pwm.yaml#
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
21 - mediatek,mt7622-pwm
22 - mediatek,mt7623-pwm
23 - mediatek,mt7628-pwm
24 - mediatek,mt7629-pwm
25 - mediatek,mt7981-pwm
[all …]
H A Dmediatek,pwm-disp.yaml4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
13 - $ref: pwm.yaml#
19 - mediatek,mt2701-disp-pwm
20 - mediatek,mt6595-disp-pwm
21 - mediatek,mt8173-disp-pwm
22 - mediatek,mt8183-disp-pwm
25 - mediatek,mt6795-disp-pwm
26 - mediatek,mt8167-disp-pwm
27 - const: mediatek,mt8173-disp-pwm
30 - mediatek,mt8186-disp-pwm
[all …]
H A Dpwm-sifive.txt1 SiFive PWM controller
3 Unlike most other PWM controllers, the SiFive PWM controller currently only
4 supports one period for all channels in the PWM. All PWMs need to run at
7 PWM RTL that corresponds to the IP block version numbers can be found
10 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
13 - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
14 Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
15 PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
16 SiFive PWM v0 IP block with no chip integration tweaks.
19 - clocks: Should contain a clock identifier for the PWM's parent clock.
[all …]
H A Datmel,at91sam-pwm.yaml5 $id: http://devicetree.org/schemas/pwm/atmel,at91sam-pwm.yaml#
8 title: Atmel/Microchip PWM controller
14 - $ref: pwm.yaml#
21 - atmel,at91sam9rl-pwm
22 - atmel,sama5d3-pwm
23 - atmel,sama5d2-pwm
24 - microchip,sam9x60-pwm
27 - microchip,sama7d65-pwm
28 - microchip,sama7g5-pwm
29 - const: atmel,sama5d2-pwm
[all …]
H A Dpxa-pwm.txt1 Marvell PWM controller
5 - "marvell,pxa250-pwm"
6 - "marvell,pxa270-pwm"
7 - "marvell,pxa168-pwm"
8 - "marvell,pxa910-pwm"
9 - reg: Physical base address and length of the registers used by the PWM channel
10 Note that one device instance must be created for each PWM that is used, so the
11 length covers only the register window for one PWM output, not that of the
12 entire PWM controller. Currently length is 0x10 for all supported devices.
13 - #pwm-cells: Should be 1. This cell is used to specify the period in
[all …]
H A Dpwm-lp3943.txt1 TI/National Semiconductor LP3943 PWM controller
4 - compatible: "ti,lp3943-pwm"
5 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a
9 - ti,pwm0 or ti,pwm1: Output pin number(s) for PWM channel 0 or 1.
17 PWM 0 is for RGB LED brightness control
18 PWM 1 is for brightness control of LP8557 backlight device
26 * PWM 0 : output 8, 9 and 10
27 * PWM 1 : output 15
29 pwm3943: pwm {
30 compatible = "ti,lp3943-pwm";
[all …]
H A Dpwm-mtk-disp.txt1 MediaTek display PWM controller
4 - compatible: should be "mediatek,<name>-disp-pwm":
5 - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6 - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7 - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
8 - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
9 - "mediatek,mt8183-disp-pwm": found on mt8183 SoC.$
11 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
13 - clocks: phandle and clock specifier of the PWM reference clock.
15 - "main": clock used to generate PWM signals.
[all …]
H A Dpwm.yaml4 $id: http://devicetree.org/schemas/pwm/pwm.yaml#
7 title: PWM controllers (providers)
16 pattern: "^pwm(@.*|-([0-9]|[1-9][0-9]+))?$"
18 "#pwm-cells":
20 Number of cells in a PWM specifier. Typically the cells represent, in
21 order: the chip-relative PWM number, the PWM period in nanoseconds and
22 optionally a number of flags (defined in <dt-bindings/pwm/pwm.h>).
25 - "#pwm-cells"
31 pwm: pwm@1c20e00 {
32 compatible = "allwinner,sun7i-a20-pwm";
[all …]
H A Dgoogle,cros-ec-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/google,cros-ec-pwm.yaml#
7 title: PWM controlled by ChromeOS EC
14 Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller
16 An EC PWM node should be only found as a sub-node of the EC node (see
20 - $ref: pwm.yaml#
25 - description: PWM controlled using EC_PWM_TYPE_GENERIC channels.
27 - const: google,cros-ec-pwm
28 - description: PWM controlled using CROS_EC_PWM_DT_<...> types.
30 - const: google,cros-ec-pwm-type
32 "#pwm-cells":
[all …]
H A Dpwm-meson.txt1 Amlogic Meson PWM Controller
5 - compatible: Shall contain "amlogic,meson8b-pwm"
6 or "amlogic,meson-gxbb-pwm"
7 or "amlogic,meson-gxbb-ao-pwm"
8 or "amlogic,meson-axg-ee-pwm"
9 or "amlogic,meson-axg-ao-pwm"
10 or "amlogic,meson-g12a-ee-pwm"
11 or "amlogic,meson-g12a-ao-pwm-ab"
12 or "amlogic,meson-g12a-ao-pwm-cd"
13 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
[all …]
H A Dmxs-pwm.yaml4 $id: http://devicetree.org/schemas/pwm/mxs-pwm.yaml#
7 title: Freescale MXS PWM controller
13 - $ref: pwm.yaml#
18 - const: fsl,imx23-pwm
21 - fsl,imx28-pwm
22 - const: fsl,imx23-pwm
30 "#pwm-cells":
33 fsl,pwm-number:
35 description: u32 value representing the number of PWM devices
41 - fsl,pwm-number
[all …]
/freebsd/share/man/man4/man4.arm/
H A Dbcm283x_pwm.432 .Nd bcm283x_pwm - driver for Raspberry Pi 2/3 PWM
39 driver provides access to the PWM engine on GPIO12 of Raspberry Pi 2 and 3 hardware.
41 The PWM hardware is controlled via the
45 dev.pwm.0.mode: 1
46 dev.pwm.0.mode2: 1
47 dev.pwm.0.freq: 125000000
48 dev.pwm.0.ratio: 2500
49 dev.pwm.0.ratio2: 2500
50 dev.pwm.0.period: 10000
51 dev.pwm.0.period2: 10000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/leds/backlight/
H A Dpwm-backlight.txt1 pwm-backlight bindings
4 - compatible: "pwm-backlight"
5 - pwms: OF device-tree PWM specification (see PWM binding[0])
9 - pwm-names: a list of names for the PWM devices specified in the
10 "pwms" property (see PWM binding[0])
13 - post-pwm-on-delay-ms: Delay in ms between setting an initial (non-zero) PWM
15 - pwm-off-delay-ms: Delay in ms between disabling the backlight using GPIO
16 and setting PWM value to 0.
19 0 will do. The actual brightness level (PWM duty cycle)
27 resolution pwm duty cycle can be used without
[all …]
/freebsd/sys/contrib/device-tree/Bindings/leds/
H A Dleds-pwm.txt1 LED connected to PWM
4 - compatible : should be "pwm-leds".
6 Each LED is represented as a sub-node of the pwm-leds device. Each
10 - pwms : PWM property to point to the PWM device (phandle)/port (id) and to
12 - pwm-names : (optional) Name to be used by the PWM subsystem for the PWM device
13 For the pwms and pwm-names property please refer to:
14 Documentation/devicetree/bindings/pwm/pwm.txt
25 twl_pwm: pwm {
27 compatible = "ti,twl6030-pwm";
28 #pwm-cells = <2>;
[all …]

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