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/linux/include/linux/
H A Dpwm.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 MODULE_IMPORT_NS("PWM");
16 * enum pwm_polarity - polarity of a PWM signal
17 * @PWM_POLARITY_NORMAL: a high signal for the duration of the duty-
19 * period
20 * @PWM_POLARITY_INVERSED: a low signal for the duration of the duty-
22 * period
30 * struct pwm_args - board-dependent PWM arguments
31 * @period: reference period
34 * This structure describes board-dependent arguments attached to a PWM
[all …]
/linux/drivers/pwm/
H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2011-2012 Avionic Design GmbH
9 #define DEFAULT_SYMBOL_NAMESPACE "PWM"
15 #include <linux/pwm.h>
24 #include <dt-bindings/pwm/pwm.h>
27 #include <trace/events/pwm.h>
36 if (chip->atomic) in pwmchip_lock()
37 spin_lock(&chip->atomic_lock); in pwmchip_lock()
39 mutex_lock(&chip->nonatomic_lock); in pwmchip_lock()
44 if (chip->atomic) in pwmchip_unlock()
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H A Dpwm-visconti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti pulse-width-modulation controller driver
5 * Copyright (c) 2020 - 2021 TOSHIBA CORPORATION
6 * Copyright (c) 2020 - 2021 Toshiba Electronic Devices & Storage Corporation
11 * - The fixed input clock is running at 1 MHz and is divided by either 1,
13 * - When the settings of the PWM are modified, the new values are shadowed
15 * running period is completed. This way the hardware switches atomically
17 * - Disabling the hardware completes the currently running period and keeps
26 #include <linux/pwm.h>
45 static int visconti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in visconti_pwm_apply() argument
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H A Dpwm-omap-dmtimer.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
15 * reloaded with the load value and the pwm output goes up.
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
24 * a period with mixed settings. Especially when period/duty_cyle
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
27 * - period for current cycle = current_period + new period
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H A Dpwm-microchip-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11 * - If the IP block is configured without "shadow registers", all register
17 * As setting the period/duty cycle takes 4 register writes, there is a window
18 * in which this races against the start of a new period
70 mchp_core_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm,bool enable,u64 period) mchp_core_pwm_enable() argument
71 mchp_core_pwm_enable(struct pwm_chip * chip,struct pwm_device * pwm,bool enable,u64 period) mchp_core_pwm_enable() argument
150 mchp_core_pwm_apply_duty(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state,u64 duty_steps,u16 period_steps) mchp_core_pwm_apply_duty() argument
273 mchp_core_pwm_apply_locked(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state) mchp_core_pwm_apply_locked() argument
359 mchp_core_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state) mchp_core_pwm_apply() argument
376 mchp_core_pwm_get_state(struct pwm_chip * chip,struct pwm_device * pwm,struct pwm_state * state) mchp_core_pwm_get_state() argument
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H A Dpwm-dwc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * DesignWare PWM Controller driver core
5 * Copyright (C) 2018-2020 Intel Corporation
20 #include <linux/pwm.h>
22 #include "pwm-dwc.h"
24 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) in __dwc_pwm_set_enable() argument
28 reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
35 dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
39 struct pwm_device *pwm, in __dwc_pwm_configure_timer() argument
48 * Calculate width of low and high period in terms of input clock in __dwc_pwm_configure_timer()
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H A Dpwm-jz4740.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
39 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
40 u32 pwm_channels_mask = GENMASK(chip->npwm - 1, 2); in jz4740_pwm_can_use_chn()
42 device_property_read_u32(pwmchip_parent(chip)->parent, in jz4740_pwm_can_use_chn()
43 "ingenic,pwm-channels-mask", in jz4740_pwm_can_use_chn()
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H A Dpwm-fsl-ftm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale FlexTimer Module (FTM) PWM Driver
5 * Copyright 2012-2013 Freescale Semiconductor, Inc.
17 #include <linux/pwm.h>
46 /* This value is valid iff a pwm is running */
47 struct fsl_pwm_periodcfg period; member
64 regmap_read(fpc->regmap, FTM_FMS, &val); in ftm_clear_write_protection()
66 regmap_set_bits(fpc->regmap, FTM_MODE, FTM_MODE_WPDIS); in ftm_clear_write_protection()
71 regmap_set_bits(fpc->regmap, FTM_FMS, FTM_FMS_WPEN); in ftm_set_write_protection()
77 if (a->clk_select != b->clk_select) in fsl_pwm_periodcfg_are_equal()
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H A Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
29 #include <linux/pwm.h>
32 /* The following is global registers for PWM controller */
40 /* The following register is PWM channel related registers */
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H A Dpwm-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pwm.h>
17 #define PWM_MODE 0x80 /* set timer in PWM mode */
21 #define PERIOD(x) (((x) * 0x10) + 0x10) macro
37 static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in bcm2835_pwm_request() argument
42 value = readl(pc->base + PWM_CONTROL); in bcm2835_pwm_request()
43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 writel(value, pc->base + PWM_CONTROL); in bcm2835_pwm_request()
50 static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) in bcm2835_pwm_free() argument
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H A Dpwm-imx-tpm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2018-2019 NXP.
6 * - The TPM counter and period counter are shared between
7 * multiple channels, so all channels should use same period
9 * - Changes to polarity cannot be latched at the time of the
10 * next period start.
11 * - Changing period and duty cycle together isn't atomic,
12 * with the wrong timing it might happen that a period is
13 * produced with old duty cycle but new period settings.
25 #include <linux/pwm.h>
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H A Dpwm-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
15 #include <linux/pwm.h>
41 unsigned long period; member
60 struct pwm_device *pwm, in rockchip_pwm_get_state() argument
64 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
70 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
74 ret = clk_enable(pc->clk); in rockchip_pwm_get_state()
78 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
80 tmp = readl_relaxed(pc->base + pc->data->regs.period); in rockchip_pwm_get_state()
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H A Dpwm-atmel-tcb.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/pwm.h>
36 unsigned div; /* PWM clock divider */
37 unsigned duty; /* PWM duty expressed in clk cycles */
38 unsigned period; /* PWM period expressed in clk cycles */ member
69 struct pwm_device *pwm) in atmel_tcb_pwm_request() argument
72 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm]; in atmel_tcb_pwm_request()
76 ret = clk_prepare_enable(tcbpwmc->clk); in atmel_tcb_pwm_request()
80 tcbpwm->duty = 0; in atmel_tcb_pwm_request()
81 tcbpwm->period = 0; in atmel_tcb_pwm_request()
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H A Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
9 * and the currently running period is not guaranteed to be completed
21 #include <linux/pwm.h>
47 #define PWM_PRD(prd) (((prd) - 1) << 16)
100 return readl(sun4ichip->base + offset); in sun4i_pwm_readl()
106 writel(val, sun4ichip->base + offset); in sun4i_pwm_writel()
110 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
118 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_get_state()
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H A Dpwm-renesas-tpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
17 #include <linux/pwm.h>
62 TPU_PIN_PWM, /* Pin is driven by PWM */
76 u16 period; member
96 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET in tpu_pwm_write()
97 + tpd->channel * TPU_CHANNEL_SIZE; in tpu_pwm_write()
105 static const char * const states[] = { "inactive", "PWM", "active" }; in tpu_pwm_set_pin()
107 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n", in tpu_pwm_set_pin()
108 tpd->channel, states[state]); in tpu_pwm_set_pin()
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H A Dpwm-bcm-iproc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pwm.h>
29 #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
50 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
52 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
62 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
64 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
70 static int iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in iproc_pwmc_get_state() argument
77 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_get_state()
79 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
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H A Dpwm-sifive.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
19 #include <linux/pwm.h>
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H A Dpwm-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM device driver for ST SoCs
5 * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
18 #include <linux/pwm.h>
59 * Each capture input can be programmed to detect rising-edge, falling-edge,
115 * Calculate the prescaler value corresponding to the period.
117 static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period, in sti_pwm_get_prescale() argument
124 clk_rate = clk_get_rate(pc->pwm_clk); in sti_pwm_get_prescale()
126 dev_err(pc->dev, "failed to get clock rate\n"); in sti_pwm_get_prescale()
127 return -EINVAL; in sti_pwm_get_prescale()
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H A Dpwm-intel-lgm.c1 // SPDX-License-Identifier: GPL-2.0
6 * - The hardware supports fixed period & configures only 2-wire mode.
7 * - Supports normal polarity. Does not support changing polarity.
8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
9 * keep track of running period.
10 * - When duty cycle is changed, PWM output may be a mix of previous setting
11 * and new setting for the first period. From second period, the output is
13 * - It is a dedicated PWM fan controller. There are no other consumers for
14 * this PWM controller.
21 #include <linux/pwm.h>
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H A Dpwm-hibvt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM Controller Driver for HiSilicon BVT SoCs
15 #include <linux/pwm.h>
82 static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_enable() argument
86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
90 static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_disable() argument
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
98 static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in hibvt_pwm_config() argument
102 u32 freq, period, duty; in hibvt_pwm_config() local
104 freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); in hibvt_pwm_config()
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H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
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/linux/drivers/clk/
H A Dclk-pwm.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * PWM (mis)used as clock output
7 #include <linux/clk-provider.h>
12 #include <linux/pwm.h>
16 struct pwm_device *pwm; member
29 return pwm_enable(clk_pwm->pwm); in clk_pwm_prepare()
36 pwm_disable(clk_pwm->pwm); in clk_pwm_unprepare()
44 return clk_pwm->fixed_rate; in clk_pwm_recalc_rate()
52 pwm_get_state(clk_pwm->pwm, &state); in clk_pwm_get_duty_cycle()
54 duty->num = state.duty_cycle; in clk_pwm_get_duty_cycle()
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/linux/Documentation/driver-api/
H A Dpwm.rst2 Pulse Width Modulation (PWM) interface
5 This provides an overview about the Linux PWM interface
9 the Linux PWM API (although they could). However, PWMs are often
12 this kind of flexibility the generic PWM API exists.
15 ----------------
17 Users of the legacy PWM API use unique IDs to refer to PWM devices.
19 Instead of referring to a PWM device via its unique ID, board setup code
20 should instead register a static mapping that can be used to match PWM
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
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/linux/drivers/staging/greybus/
H A Dpwm.c1 // SPDX-License-Identifier: GPL-2.0
3 * PWM Greybus driver.
12 #include <linux/pwm.h>
38 * The request returns the highest allowed PWM id parameter. So add one in gb_pwm_get_npwm()
58 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_ACTIVATE, in gb_pwm_activate_operation()
80 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_DEACTIVATE, in gb_pwm_deactivate_operation()
89 u8 which, u32 duty, u32 period) in gb_pwm_config_operation() argument
98 request.period = cpu_to_le32(period); in gb_pwm_config_operation()
105 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_CONFIG, in gb_pwm_config_operation()
129 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_POLARITY, in gb_pwm_set_polarity_operation()
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/linux/drivers/input/misc/
H A Dpwm-beeper.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * PWM beeper driver
14 #include <linux/pwm.h>
20 struct pwm_device *pwm; member
23 unsigned long period; member
31 static int pwm_beeper_on(struct pwm_beeper *beeper, unsigned long period) in pwm_beeper_on() argument
36 pwm_get_state(beeper->pwm, &state); in pwm_beeper_on()
39 state.period = period; in pwm_beeper_on()
42 error = pwm_apply_might_sleep(beeper->pwm, &state); in pwm_beeper_on()
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