Home
last modified time | relevance | path

Searched +full:pwm +full:- +full:period (Results 1 – 25 of 157) sorted by relevance

1234567

/linux/drivers/pwm/
H A Dpwm-microchip-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2021-2023 Microchip Corporation. All rights reserved.
8 * https://www.microsemi.com/document-portal/doc_download/1245275-corepwm-hb
11 * - If the IP block is configured without "shadow registers", all register
17 * As setting the period/duty cycle takes 4 register writes, there is a window
18 * in which this races against the start of a new period.
19 * - The IP block has no concept of a duty cycle, only rising/falling edges of
23 * period. Therefore to get a 0% waveform, the output is set the max high/low
25 * If the duty cycle is 0%, and the requested period is less than the
26 * available period resolution, this will manifest as a ~100% waveform (with
[all …]
H A Dpwm-visconti.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Toshiba Visconti pulse-width-modulation controller driver
5 * Copyright (c) 2020 - 2021 TOSHIBA CORPORATION
6 * Copyright (c) 2020 - 2021 Toshiba Electronic Devices & Storage Corporation
11 * - The fixed input clock is running at 1 MHz and is divided by either 1,
13 * - When the settings of the PWM are modified, the new values are shadowed
15 * running period is completed. This way the hardware switches atomically
17 * - Disabling the hardware completes the currently running period and keeps
26 #include <linux/pwm.h>
45 static int visconti_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in visconti_pwm_apply() argument
[all …]
H A Dpwm-omap-dmtimer.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Also based on pwm-samsung.c
13 * PWM driver / controller, using the OMAP's dual-mode timers
15 * reloaded with the load value and the pwm output goes up.
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
24 * a period with mixed settings. Especially when period/duty_cyle
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
27 * - period for current cycle = current_period + new period
[all …]
H A Dpwm-dwc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * DesignWare PWM Controller driver core
5 * Copyright (C) 2018-2020 Intel Corporation
20 #include <linux/pwm.h>
22 #include "pwm-dwc.h"
24 static void __dwc_pwm_set_enable(struct dwc_pwm *dwc, int pwm, int enabled) in __dwc_pwm_set_enable() argument
28 reg = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
35 dwc_pwm_writel(dwc, reg, DWC_TIM_CTRL(pwm)); in __dwc_pwm_set_enable()
39 struct pwm_device *pwm, in __dwc_pwm_configure_timer() argument
48 * Calculate width of low and high period in terms of input clock in __dwc_pwm_configure_timer()
[all …]
H A Dpwm-jz4740.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
39 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
40 u32 pwm_channels_mask = GENMASK(chip->npwm - 1, 2); in jz4740_pwm_can_use_chn()
42 device_property_read_u32(pwmchip_parent(chip)->parent, in jz4740_pwm_can_use_chn()
43 "ingenic,pwm-channels-mask", in jz4740_pwm_can_use_chn()
[all …]
H A Dpwm-sophgo-sg2042.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 PWM Controller Driver
9 * - After reset, the output of the PWM channel is always high.
10 * The value of HLPERIOD/PERIOD is 0.
11 * - When HLPERIOD or PERIOD is reconfigured, PWM will start to
13 * the running period.
14 * - When PERIOD and HLPERIOD is set to 0, the PWM wave output will
16 * - SG2044 supports both polarities, SG2042 only normal polarity.
18 * [1]:https://github.com/sophgo/sophgo-doc/tree/main/SG2042/TRM
27 #include <linux/pwm.h>
[all …]
H A Dpwm-atmel.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Links to reference manuals for the supported PWM chips can be found in
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
29 #include <linux/pwm.h>
32 /* The following is global registers for PWM controller */
40 /* The following register is PWM channel related registers */
[all …]
H A Dpwm-bcm2835.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/pwm.h>
17 #define PWM_MODE 0x80 /* set timer in PWM mode */
21 #define PERIOD(x) (((x) * 0x10) + 0x10) macro
37 static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) in bcm2835_pwm_request() argument
42 value = readl(pc->base + PWM_CONTROL); in bcm2835_pwm_request()
43 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
44 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm)); in bcm2835_pwm_request()
45 writel(value, pc->base + PWM_CONTROL); in bcm2835_pwm_request()
50 static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) in bcm2835_pwm_free() argument
[all …]
H A Dpwm-atmel-tcb.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/pwm.h>
36 unsigned div; /* PWM clock divider */
37 unsigned duty; /* PWM duty expressed in clk cycles */
38 unsigned period; /* PWM period expressed in clk cycles */ member
69 struct pwm_device *pwm) in atmel_tcb_pwm_request() argument
72 struct atmel_tcb_pwm_device *tcbpwm = &tcbpwmc->pwms[pwm->hwpwm]; in atmel_tcb_pwm_request()
76 ret = clk_prepare_enable(tcbpwmc->clk); in atmel_tcb_pwm_request()
80 tcbpwm->duty = 0; in atmel_tcb_pwm_request()
81 tcbpwm->period = 0; in atmel_tcb_pwm_request()
[all …]
H A Dpwm-sun4i.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
8 * - When outputing the source clock directly, the PWM logic will be bypassed
9 * and the currently running period is not guaranteed to be completed
21 #include <linux/pwm.h>
46 #define PWM_PRD(prd) (((prd) - 1) << 16)
98 return readl(sun4ichip->base + offset); in sun4i_pwm_readl()
104 writel(val, sun4ichip->base + offset); in sun4i_pwm_writel()
108 struct pwm_device *pwm, in sun4i_pwm_get_state() argument
116 clk_rate = clk_get_rate(sun4ichip->clk); in sun4i_pwm_get_state()
[all …]
H A Dpwm-renesas-tpu.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Mobile TPU PWM driver
17 #include <linux/pwm.h>
62 TPU_PIN_PWM, /* Pin is driven by PWM */
76 u16 period; member
96 void __iomem *base = tpd->tpu->base + TPU_CHANNEL_OFFSET in tpu_pwm_write()
97 + tpd->channel * TPU_CHANNEL_SIZE; in tpu_pwm_write()
105 static const char * const states[] = { "inactive", "PWM", "active" }; in tpu_pwm_set_pin()
107 dev_dbg(&tpd->tpu->pdev->dev, "%u: configuring pin as %s\n", in tpu_pwm_set_pin()
108 tpd->channel, states[state]); in tpu_pwm_set_pin()
[all …]
H A Dpwm-sti.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM device driver for ST SoCs
5 * Copyright (C) 2013-2016 STMicroelectronics (R&D) Limited
18 #include <linux/pwm.h>
59 * Each capture input can be programmed to detect rising-edge, falling-edge,
114 * Calculate the prescaler value corresponding to the period.
116 static int sti_pwm_get_prescale(struct sti_pwm_chip *pc, unsigned long period, in sti_pwm_get_prescale() argument
123 clk_rate = clk_get_rate(pc->pwm_clk); in sti_pwm_get_prescale()
125 dev_err(pc->dev, "failed to get clock rate\n"); in sti_pwm_get_prescale()
126 return -EINVAL; in sti_pwm_get_prescale()
[all …]
H A Dpwm-bcm-iproc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/pwm.h>
29 #define IPROC_PWM_PRESCALE_SHIFT(ch) ((3 - (ch)) * \
50 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
52 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_enable()
62 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
64 writel(value, ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_disable()
70 static int iproc_pwmc_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in iproc_pwmc_get_state() argument
77 value = readl(ip->base + IPROC_PWM_CTRL_OFFSET); in iproc_pwmc_get_state()
79 if (value & BIT(IPROC_PWM_CTRL_EN_SHIFT(pwm->hwpwm))) in iproc_pwmc_get_state()
[all …]
H A Dpwm-sifive.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
7 * PWM output inversion: According to the SiFive Reference manual
12 * hard-tied to 0 (XNOR), which effectively inverts the comparison so that
16 * (low) period of the pulse, not the active time exactly opposite to what
21 * **active-high** PWM interface.
25 * - When changing both duty cycle and period, we cannot prevent in
26 * software that the output might produce a period with mixed
[all …]
H A Dpwm-intel-lgm.c1 // SPDX-License-Identifier: GPL-2.0
6 * - The hardware supports fixed period & configures only 2-wire mode.
7 * - Supports normal polarity. Does not support changing polarity.
8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
9 * keep track of running period.
10 * - When duty cycle is changed, PWM output may be a mix of previous setting
11 * and new setting for the first period. From second period, the output is
13 * - It is a dedicated PWM fan controller. There are no other consumers for
14 * this PWM controller.
21 #include <linux/pwm.h>
[all …]
H A Dpwm-hibvt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * PWM Controller Driver for HiSilicon BVT SoCs
15 #include <linux/pwm.h>
82 static void hibvt_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_enable() argument
86 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_enable()
90 static void hibvt_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) in hibvt_pwm_disable() argument
94 hibvt_pwm_set_bits(hi_pwm_chip->base, PWM_CTRL_ADDR(pwm->hwpwm), in hibvt_pwm_disable()
98 static void hibvt_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, in hibvt_pwm_config() argument
102 u32 freq, period, duty; in hibvt_pwm_config() local
104 freq = div_u64(clk_get_rate(hi_pwm_chip->clk), 1000000); in hibvt_pwm_config()
[all …]
H A Dpwm-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PWM driver for Rockchip SoCs
17 #include <linux/pwm.h>
43 unsigned long period; member
62 struct pwm_device *pwm, in rockchip_pwm_get_state() argument
66 u64 prescaled_ns = (u64)pc->data->prescaler * NSEC_PER_SEC; in rockchip_pwm_get_state()
67 u32 enable_conf = pc->data->enable_conf; in rockchip_pwm_get_state()
73 ret = clk_enable(pc->pclk); in rockchip_pwm_get_state()
77 ret = clk_enable(pc->clk); in rockchip_pwm_get_state()
81 clk_rate = clk_get_rate(pc->clk); in rockchip_pwm_get_state()
[all …]
H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
[all …]
H A Dpwm-twl-led.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * This driver is a complete rewrite of the former pwm-twl6030.c authorded by:
15 * - The twl6030 hardware only supports two period lengths (128 clock ticks and
17 * - The hardware doesn't support ON = 0, so the active part of a period doesn't
19 * - The hardware could support inverted polarity (with a similar limitation as
21 * - The hardware emits a constant low output when disabled.
22 * - A request for .duty_cycle = 0 results in an output wave with one active
23 * clock tick per period. This should better use the disabled state.
24 * - The driver only implements setting the relative duty cycle.
25 * - The driver doesn't implement .get_state().
[all …]
H A Dpwm-crc.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/pwm.h>
28 * struct crystalcove_pwm - Crystal Cove PWM controller
45 /* clk_div 1 - 128, maps to register values 0-127 */ in crc_pwm_calc_clk_div()
47 clk_div--; in crc_pwm_calc_clk_div()
52 static int crc_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, in crc_pwm_apply() argument
59 if (state->period > PWM_MAX_PERIOD_NS) { in crc_pwm_apply()
60 dev_err(dev, "un-supported period_ns\n"); in crc_pwm_apply()
61 return -EINVAL; in crc_pwm_apply()
64 if (state->polarity != PWM_POLARITY_NORMAL) in crc_pwm_apply()
[all …]
H A Dpwm-meson.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * PWM controller driver for Amlogic Meson SoCs.
5 * This PWM is only a set of Gates, Dividers and Counters:
6 * PWM output is achieved by calculating a clock that permits calculating
8 * N cycles for the first half period.
9 * Partly the hardware has no "polarity" setting. This driver reverses the period
13 * Setting the duty cycle will disable and re-enable the PWM output.
14 * Disabling the PWM stops the output immediately (without waiting for the
15 * current period to complete first).
17 * The public S912 (GXM) datasheet contains some documentation for this PWM
[all …]
/linux/Documentation/driver-api/
H A Dpwm.rst2 Pulse Width Modulation (PWM) interface
5 This provides an overview about the Linux PWM interface
9 the Linux PWM API (although they could). However, PWMs are often
12 this kind of flexibility the generic PWM API exists.
15 ----------------
17 Users of the legacy PWM API use unique IDs to refer to PWM devices.
19 Instead of referring to a PWM device via its unique ID, board setup code
20 should instead register a static mapping that can be used to match PWM
24 PWM_LOOKUP("tegra-pwm", 0, "pwm-backlight", NULL,
36 ----------
[all …]
/linux/drivers/staging/greybus/
H A Dpwm.c1 // SPDX-License-Identifier: GPL-2.0
3 * PWM Greybus driver.
12 #include <linux/pwm.h>
38 * The request returns the highest allowed PWM id parameter. So add one in gb_pwm_get_npwm()
58 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_ACTIVATE, in gb_pwm_activate_operation()
80 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_DEACTIVATE, in gb_pwm_deactivate_operation()
89 u8 which, u32 duty, u32 period) in gb_pwm_config_operation() argument
98 request.period = cpu_to_le32(period); in gb_pwm_config_operation()
105 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_CONFIG, in gb_pwm_config_operation()
129 ret = gb_operation_sync(pwmc->connection, GB_PWM_TYPE_POLARITY, in gb_pwm_set_polarity_operation()
[all …]
/linux/drivers/input/misc/
H A Dpwm-beeper.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * PWM beeper driver
14 #include <linux/pwm.h>
20 struct pwm_device *pwm; member
23 unsigned long period; member
31 static int pwm_beeper_on(struct pwm_beeper *beeper, unsigned long period) in pwm_beeper_on() argument
36 pwm_get_state(beeper->pwm, &state); in pwm_beeper_on()
39 state.period = period; in pwm_beeper_on()
42 error = pwm_apply_might_sleep(beeper->pwm, &state); in pwm_beeper_on()
[all …]
/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
16 run at the same period. The period also has significant restrictions on
18 achievable period. PWM RTL that corresponds to the IP block version
[all …]

1234567