| /freebsd/share/man/man4/man4.arm/ |
| H A D | bcm283x_pwm.4 | 2 .\" SPDX-License-Identifier: BSD-2-Clause
4 .\" Copyright (c) 2017 Poul-Henning Kamp <phk@FreeBSD.org>
32 .Nd bcm283x_pwm - driver for Raspberry Pi 2/3 PWM
39 driver provides access to the PWM engine on GPIO12 of Raspberry Pi 2 and 3 hardware.
41 The PWM hardware is controlled via the
44 .Bd -literal
45 dev.pwm.0.mode: 1
46 dev.pwm.0.mode2: 1
47 dev.pwm.0.freq: 125000000
48 dev.pwm.0.ratio: 2500
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| /freebsd/usr.sbin/pwm/ |
| H A D | pwm.8 | 27 .Nm pwm
28 .Nd configure PWM (Pulse Width Modulation) hardware
37 .Op Fl p Ar period
42 utility can be used to configure pwm hardware.
47 Some PWM hardware supports multiple output channels within a single
50 instance controls a single PWM channel.
54 .Pa /dev/pwm/pwmcX.Y ,
62 .Bl -tag -width "-f device"
66 .Pa /dev/pwm/pwmc0.0
69 .Pa /dev/pwm
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| H A D | pwm.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
32 #include <dev/pwm/pwmc.h>
51 static char device_name[PATH_MAX] = "/dev/pwm/pwmc0.0";
60 snprintf(device_name, sizeof(device_name), "/dev/pwm/%s", name); in set_device_name()
67 fprintf(stderr, "\tpwm [-f dev] -C\n"); in usage()
68 fprintf(stderr, "\tpwm [-f dev] [-D | -E] [-I] [-p period] [-d duty[%%]]\n"); in usage()
77 u_int period, duty; in main() local
86 fd = -1; in main()
87 period = duty = -1; in main()
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| /freebsd/sys/contrib/device-tree/Bindings/pwm/ |
| H A D | pwm-sifive.txt | 1 SiFive PWM controller
3 Unlike most other PWM controllers, the SiFive PWM controller currently only
4 supports one period for all channels in the PWM. All PWMs need to run at
5 the same period. The period also has significant restrictions on the values
6 it can achieve, which the driver rounds to the nearest achievable period.
7 PWM RTL that corresponds to the IP block version numbers can be found
10 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
13 - compatible: Should be "sifive,<chip>-pwm" and "sifive,pwm<version>".
14 Supported compatible strings are: "sifive,fu540-c000-pwm" for the SiFive
15 PWM v0 as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
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| H A D | pwm-sifive.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
16 run at the same period. The period also has significant restrictions on
18 achievable period. PWM RTL that corresponds to the IP block version
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| H A D | pwm-bcm2835.txt | 1 BCM2835 PWM controller (Raspberry Pi controller)
4 - compatible: should be "brcm,bcm2835-pwm"
5 - reg: physical base address and length of the controller's registers
6 - clocks: This clock defines the base clock frequency of the PWM hardware
7 system, the period and the duty_cycle of the PWM signal is a multiple of
8 the base period.
9 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
14 pwm@2020c000 {
15 compatible = "brcm,bcm2835-pwm";
18 #pwm-cells = <3>;
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| H A D | imx-tpm-pwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX TPM PWM controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 The TPM counter and period counter are shared between multiple
16 channels, so all channels should use same period setting.
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| H A D | microchip,corepwm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Conor Dooley <conor.dooley@microchip.com>
16 https://www.microsemi.com/existing-parts/parts/152118
19 - $ref: pwm.yaml#
24 - const: microchip,corepwm-rtl-v4
32 "#pwm-cells":
37 microchip,sync-update-mask:
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| H A D | pxa-pwm.txt | 1 Marvell PWM controller
4 - compatible: should be one or more of:
5 - "marvell,pxa250-pwm"
6 - "marvell,pxa270-pwm"
7 - "marvell,pxa168-pwm"
8 - "marvell,pxa910-pwm"
9 - reg: Physical base address and length of the registers used by the PWM channel
10 Note that one device instance must be created for each PWM that is used, so the
11 length covers only the register window for one PWM output, not that of the
12 entire PWM controller. Currently length is 0x10 for all supported devices.
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| H A D | pwm.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pwm/pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PWM controllers (providers)
10 - Thierry Reding <thierry.reding@gmail.com>
16 pattern: "^pwm(@.*|-([0-9]|[1-9][0-9]+))?$"
18 "#pwm-cells":
20 Number of cells in a PWM specifier. Typically the cells represent, in
21 order: the chip-relative PWM number, the PWM period in nanoseconds and
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| H A D | pwm-zx.txt | 1 ZTE ZX PWM controller
4 - compatible: Should be "zte,zx296718-pwm".
5 - reg: Physical base address and length of the controller's registers.
6 - clocks : The phandle and specifier referencing the controller's clocks.
7 - clock-names: "pclk" for PCLK, "wclk" for WCLK to the PWM controller. The
9 calculating period and duty cycles.
10 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
15 pwm: pwm@1439000 {
16 compatible = "zte,zx296718-pwm";
20 clock-names = "pclk", "wclk";
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| /freebsd/sys/arm/broadcom/bcm2835/ |
| H A D | bcm2835_pwm.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2017 Poul-Henning Kamp <phk@FreeBSD.org>
49 {"broadcom,bcm2835-pwm", 1},
50 {"brcm,bcm2835-pwm", 1},
64 uint32_t period; /* channel 1 */ member
73 bus_space_write_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off, _val)
75 bus_space_read_4(_sc->sc_m_bst, _sc->sc_m_bsh, _off)
77 bus_space_write_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off, _val)
79 bus_space_read_4(_sc->sc_c_bst, _sc->sc_c_bsh, _off)
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| /freebsd/share/man/man9/ |
| H A D | pwmbus.9 | 38 .Cd "device pwm"
41 .Fn PWMBUS_CHANNEL_CONFIG "device_t bus" "u_int channel" "u_int period" "u_int duty"
47 .Fn PWMBUS_CHANNEL_GET_CONFIG "device_t bus" "u_int channel" "u_int *period" "u_int *duty"
55 The PWMBUS (Pulse-Width Modulation) interface allows a device driver to
62 .Va period
63 argument is the duration in nanoseconds of one complete on-off cycle, and the
67 Some PWM hardware is organized as a single controller with multiple channels.
71 In such cases, changing the period or duty cycle of any one channel may affect
73 Consult the documentation for the underlying PWM hardware device driver for
76 .Bl -tag -width indent
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| /freebsd/share/man/man4/ |
| H A D | pwmc.4 | 30 .Nd PWM (Pulse Width Modulation) control device driver
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
49 driver provides device-control access to a channel of PWM hardware.
52 device is associated with a single PWM output channel.
54 Some PWM hardware is organized with multiple channels sharing a
58 instance will exist for each channel, but changing the period or
61 Consult the documentation for the underlying PWM hardware device driver
67 .Pa /dev/pwm/pwmcX.Y
70 is a sequential number assigned to each PWM hardware controller
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| /freebsd/sys/dev/pwm/controller/rockchip/ |
| H A D | rk_pwm.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
70 /* PWM Output Alignment */
97 { "rockchip,rk3288-pwm", 1 },
98 { "rockchip,rk3399-pwm", 1 },
104 { -1, 0 }
114 unsigned int period; member
123 #define RK_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))
124 #define RK_PWM_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
136 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in rk_pwm_probe()
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | pwm-clock.txt | 1 Binding for an external clock signal driven by a PWM pin.
3 This binding uses the common clock binding[1] and the common PWM binding[2].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
6 [2] Documentation/devicetree/bindings/pwm/pwm.txt
9 - compatible : shall be "pwm-clock".
10 - #clock-cells : from common clock binding; shall be set to 0.
11 - pwms : from common PWM binding; this determines the clock frequency
12 via the period given in the PWM specifier.
15 - clock-output-names : From common clock binding.
16 - clock-frequency : Exact output frequency, in case the PWM period
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| H A D | nvidia,tegra124-dfll.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
19 - registers for the integrated I2C master controller.
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| /freebsd/sys/dev/pwm/ |
| H A D | pwm_backlight.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
54 #include <dev/pwm/ofw_pwm.h>
70 uint64_t period; member
78 { "pwm-backlight", 1 },
86 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in pwm_backlight_probe()
89 device_set_desc(dev, "PWM Backlight"); in pwm_backlight_probe()
103 rv = pwm_get_by_ofw_propidx(dev, node, "pwms", 0, &sc->channel); in pwm_backlight_attach()
105 device_printf(dev, "Cannot map pwm channel %d\n", rv); in pwm_backlight_attach()
109 if (regulator_get_by_ofw_property(dev, 0, "power-supply", in pwm_backlight_attach()
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| H A D | pwmbus_if.m | 1 #-
2 # SPDX-License-Identifier: BSD-2-Clause
51 # Config the period (Total number of cycle in ns) and
57 u_int period;
62 # Get the period (Total number of cycle in ns) and
68 u_int *period;
91 # Enable the pwm output
100 # Is the pwm output enabled
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| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | ti,tas5086.txt | 1 Texas Instruments TAS5086 6-channel PWM Processor
5 - compatible: Should contain "ti,tas5086".
6 - reg: The i2c address. Should contain <0x1b>.
10 - reset-gpio: A GPIO spec to define which pin is connected to the
14 - ti,charge-period: This property should contain the time in microseconds
15 that closely matches the external single-ended
16 split-capacitor charge period. The hardware chip
17 waits for this period of time before starting the
18 PWM signals. This helps reduce pops and clicks.
23 - ti,mid-z-channel-X: Boolean properties, X being a number from 1 to 6.
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| /freebsd/sys/arm/ti/am335x/ |
| H A D | am335x_ehrpwm.c | 1 /*-
44 #include <dev/pwm/pwmc.h>
51 * Enhanced resolution PWM driver. Many of the advanced featues of the hardware
53 * variable-duty-cycle PWM output.
62 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
63 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
64 #define PWM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
65 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
66 device_get_nameunit(_sc->sc_dev), "am335x_ehrpwm softc", MTX_DEF)
67 #define PWM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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| /freebsd/sys/contrib/device-tree/Bindings/leds/backlight/ |
| H A D | lp855x-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/lp855x-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Artur Weber <aweber.kernel@gmail.com>
15 - ti,lp8550
16 - ti,lp8551
17 - ti,lp8552
18 - ti,lp8553
19 - ti,lp8555
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| H A D | lp855x.txt | 4 - compatible: "ti,lp8550", "ti,lp8551", "ti,lp8552", "ti,lp8553",
6 - reg: I2C slave address (u8)
7 - dev-ctrl: Value of DEVICE CONTROL register (u8). It depends on the device.
10 - bl-name: Backlight device name (string)
11 - init-brt: Initial value of backlight brightness (u8)
12 - pwm-period: PWM period value. Set only PWM input mode used (u32)
13 - rom-addr: Register address of ROM area to be updated (u8)
14 - rom-val: Register value to be updated (u8)
15 - power-supply: Regulator which controls the 3V rail
16 - enable-supply: Regulator which controls the EN/VDDIO input
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | ssd1307fb.txt | 4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
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| /freebsd/sys/dev/pwm/controller/allwinner/ |
| H A D | aw_pwm.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
67 { "allwinner,sun5i-a13-pwm", 1 },
68 { "allwinner,sun8i-h3-pwm", 1 },
74 { -1, 0 }
84 unsigned int period; member
109 #define AW_PWM_READ(sc, reg) bus_read_4((sc)->res, (reg))
110 #define AW_PWM_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
122 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in aw_pwm_probe()
125 device_set_desc(dev, "Allwinner PWM"); in aw_pwm_probe()
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