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/linux/drivers/pwm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 menuconfig PWM config
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
14 This framework provides a generic interface to PWM devices
16 to register and unregister a PWM chip, an abstraction of a PWM
17 controller, that supports one or more PWM devices. Client
18 drivers can request PWM devices and use the generic framework
21 This generic framework replaces the legacy PWM framework which
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H A Dpwm-lpss-platform.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Low Power Subsystem PWM controller driver
7 * Derived from the original pwm-lpss.c
17 #include "pwm-lpss.h"
26 info = device_get_match_data(&pdev->dev); in pwm_lpss_probe_platform()
28 return -ENODEV; in pwm_lpss_probe_platform()
34 chip = devm_pwm_lpss_probe(&pdev->dev, base, info); in pwm_lpss_probe_platform()
39 * On Cherry Trail devices the GFX0._PS0 AML checks if the controller in pwm_lpss_probe_platform()
41 * believes is the correct state to the PWM controller. in pwm_lpss_probe_platform()
42 * Because of this we must disallow direct-complete, which keeps the in pwm_lpss_probe_platform()
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H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
17 * frequency for PWM output. The maximum output frequency that can be
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k0500.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
27 ref_100m: clock-ref-100m {
28 compatible = "fixed-clock";
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H A Dloongson-2k2000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
34 ref_100m: clock-ref-100m {
35 compatible = "fixed-clock";
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/linux/Documentation/devicetree/bindings/pwm/
H A Dmediatek,mt2712-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,mt2712-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek PWM Controller
10 - John Crispin <john@phrozen.org>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2712-pwm
20 - mediatek,mt6795-pwm
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H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
14 (controller specific)
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H A Dpwm-hibvt.txt1 Hisilicon PWM controller
4 -compatible: should contain one SoC specific compatible string
6 "hisilicon,hi3516cv300-pwm"
7 "hisilicon,hi3519v100-pwm"
8 "hisilicon,hi3559v100-shub-pwm"
9 "hisilicon,hi3559v100-pwm
10 - reg: physical base address and length of the controller's registers.
11 - clocks: phandle and clock specifier of the PWM reference clock.
12 - resets: phandle and reset specifier for the PWM controller reset.
13 - #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of
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H A Dmediatek,pwm-disp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek DISP_PWM Controller
10 - Jitao Shi <jitao.shi@mediatek.com>
13 - $ref: pwm.yaml#
18 - enum:
19 - mediatek,mt2701-disp-pwm
20 - mediatek,mt6595-disp-pwm
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H A Datmel,hlcdc-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/atmel,hlcdc-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel's HLCDC's PWM controller
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
15 The LCDC integrates a Pulse Width Modulation (PWM) Controller. This block
17 display's contrast by software. LCDC_PWM is an 8-bit PWM signal that can be
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H A Dopencores,pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pwm/opencores,pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: OpenCores PWM controller
10 - William Qiu <william.qiu@starfivetech.com>
13 The OpenCores PTC ip core contains a PWM controller. When operating in PWM
14 mode, the PTC core generates binary signal with user-programmable low and
15 high periods. All PTC counters and registers are 32-bit.
18 - $ref: pwm.yaml#
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H A Dspear-pwm.txt1 == ST SPEAr SoC PWM controller ==
4 - compatible: should be one of:
5 - "st,spear320-pwm"
6 - "st,spear1340-pwm"
7 - reg: physical base address and length of the controller's registers
8 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
13 pwm: pwm@a8000000 {
14 compatible ="st,spear320-pwm";
16 #pwm-cells = <2>;
H A Dpwm-sifive.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive PWM controller
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 Unlike most other PWM controllers, the SiFive PWM controller currently
15 only supports one period for all channels in the PWM. All PWMs need to
18 achievable period. PWM RTL that corresponds to the IP block version
19 numbers can be found here -
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H A Dcirrus,clps711x-pwm.txt1 * Cirris Logic CLPS711X PWM controller
4 - compatible: Shall contain "cirrus,ep7209-pwm".
5 - reg: Physical base address and length of the controller's registers.
6 - clocks: phandle + clock specifier pair of the PWM reference clock.
7 - #pwm-cells: Should be 1. The cell specifies the index of the channel.
10 pwm: pwm@80000400 {
11 compatible = "cirrus,ep7312-pwm", "cirrus,ep7209-pwm";
14 #pwm-cells = <1>;
H A Dloongson,ls7a-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PWM Controller
10 - Binbin Zhou <zhoubinbin@loongson.cn>
13 The Loongson PWM has one pulse width output signal and one pulse input
15 It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips.
18 - $ref: pwm.yaml#
23 - const: loongson,ls7a-pwm
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H A Dsophgo,sg2042-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 PWM controller
10 - Chen Wang <unicorn_wang@outlook.com>
13 This controller contains 4 channels which can generate PWM waveforms.
16 - $ref: pwm.yaml#
21 - sophgo,sg2042-pwm
22 - sophgo,sg2044-pwm
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/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
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H A Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
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/linux/Documentation/devicetree/bindings/mfd/
H A Dairoha,en7581-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/airoha,en7581-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 GPIO System Controller
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Lorenzo Bianconi <lorenzo@kernel.org>
14 Airoha EN7581 SoC GPIO system controller which provided a register map
15 for controlling the GPIO, pins and PWM of the SoC.
20 - const: airoha,en7581-gpio-sysctl
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H A Dnetronix,ntxec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Netronix Embedded Controller
10 - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
13 This EC is found in e-book readers of multiple brands (e.g. Kobo, Tolino), and
22 - description: The I2C address of the EC
24 system-power-controller:
26 description: See Documentation/devicetree/bindings/power/power-controller.txt
33 "#pwm-cells":
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H A Dst,stmpe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 touchscreen, ADC, PWM or rotator. It can contain one or several different
15 - Linus Walleij <linusw@kernel.org>
18 - $ref: /schemas/spi/spi-peripheral-props.yaml#
23 - st,stmpe601
24 - st,stmpe801
25 - st,stmpe811
26 - st,stmpe1600
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/linux/arch/arm/boot/dts/renesas/
H A Dr8a7779.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H1 (R8A77790) SoC
9 #include <dt-bindings/clock/r8a7779-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7779-sysc.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 lsio_bus_clk: clock-lsio-bus {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <100000000>;
14 clock-output-names = "lsio_bus_clk";
18 compatible = "simple-bus";
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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dpptable_v1_0.h35 …AMETERS_NOFAN 0x80 /* No fan is connected to this controller. */
43 …* Thermal controller 'combo type' to use an external controller for Fan control and an internal co…
46 * The driver can pick the correct internal controller based on the ASIC.
49 …LCONTROLLER_ADT7473_WITH_INTERNAL 0x89 /* ADT7473 Fan Control + Internal Thermal Controller */
50 …LCONTROLLER_EMC2103_WITH_INTERNAL 0x8D /* EMC2103 Fan Control + Internal Thermal Controller */
245 ULONG ulDClk; /* UVD D-clock */
246 ULONG ulVClk; /* UVD V-clock */
274 …sTMin; /* The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. */
277 USHORT usPWMMin; /* The minimum PWM value in percent (0.01% increments). */
278 USHORT usPWMMed; /* The PWM value (in percent) at TMed. */
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/linux/arch/arm64/boot/dts/marvell/mmp/
H A Dpxa1908.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/marvell,pxa1908.h>
6 #include <dt-bindings/power/marvell,pxa1908-power.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
13 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <0>;
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