| /linux/tools/perf/pmu-events/arch/powerpc/power9/ |
| H A D | other.json | 45 …"BriefDescription": "The processor's data cache was reloaded from a location other than the local …
50 …dified (M) data from another core's ECO L3 on the same chip due to a data side request. When using…
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
95 …"BriefDescription": "The processor's Instruction cache was reloaded from the local chip's Memory d…
145 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
200 "BriefDescription": "Read-write data cache collisions"
255 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit st…
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
[all …]
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| /linux/arch/arm/kernel/ |
| H A D | head-nommu.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
16 #include <asm/asm-offsets.h>
25 * ---------------------------
28 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
31 * See linux/arch/arm/tools/mach-types for the complete list of machine
46 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
[all …]
|
| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | other.json | 11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
17 …cles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 belong to lpar1, threads 4-5 belong …
113 …to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that re…
161 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
167 …ed. I-form branches do not set this event. In addition, B-form branches which do not use the BHT d…
197 …ional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set thi…
203 …ional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set thi…
215 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
221 …t used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch …
359 "BriefDescription": "IFU Finished a (non-branch) instruction",
[all …]
|
| /linux/drivers/irqchip/ |
| H A D | irq-imx-mu-msi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 * Based on drivers/mailbox/imx-mailbox.c
27 #include <linux/irqchip/irq-msi-lib.h>
52 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
53 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
75 iowrite32(val, msi_data->regs + offs); in imx_mu_write()
80 return ioread32(msi_data->regs + offs); in imx_mu_read()
88 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw()
89 val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
92 imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
[all …]
|
| /linux/drivers/eisa/ |
| H A D | eisa.ids | 6 # Marc Zyngier <maz@wild-wind.fr.eu.org>
10 ABP0510 "Advansys ABP-510 ISA SCSI Host Adapter"
11 ABP0540 "Advansys ABP-540/542 ISA SCSI Host Adapter"
12 ABP7401 "AdvanSys ABP-740/742 EISA Single Channel SCSI Host Adapter"
13 ABP7501 "AdvanSys ABP-750/752 EISA Dual Channel SCSI Host Adapter"
14 ACC1200 "ACCTON EtherCombo-32 Ethernet Adapter"
15 ACC120A "ACCTON EtherCombo-32 Ethernet Adapter"
25 ACE7010 "ACME Multi-Function Board"
39 ACR1711 "AcerFrame 1000 486/33 SYSTEM-2"
41 ACR3211 "AcerFrame 3000MP 486 SYSTEM-1"
[all …]
|
| /linux/Documentation/arch/arm/ |
| H A D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
[all …]
|
| /linux/Documentation/input/devices/ |
| H A D | walkera0701.rst | 2 Walkera WK-0701 transmitter
5 Walkera WK-0701 transmitter is supplied with a ready to fly Walkera
10 http://zub.fei.tuke.sk/walkera-wk0701/
13 cg-clone http://zub.fei.tuke.sk/GIT/walkera0701-joystick
19 At back side of transmitter S-video connector can be found. Modulation
20 pulses from processor to HF part can be found at pin 2 of this connector,
26 Walkera WK-0701 TX S-VIDEO connector::
28 (back side of TX)
29 __ __ S-video: canon25
34 | [___] | |/| B |\
[all …]
|
| /linux/Documentation/core-api/ |
| H A D | cachetlb.rst | 9 describes its intended purpose, and what side effect is expected
12 The side effects described below are stated for a uniprocessor
13 implementation, and what is to happen on that single processor. The
15 definition such that the side effect for a particular interface occurs
25 virtual-->physical address translations obtained from the software
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
62 virtual addresses in the range 'start' to 'end-1'.
78 address space is available via vma->vm_mm. Also, one may
79 test (vma->vm_flags & VM_EXEC) to see if this region is
[all …]
|
| /linux/arch/arm/mach-at91/ |
| H A D | pm_suspend.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-at91/pm_slow_clock.S
13 #include "pm_data-offsets.h"
16 .arch armv7-a
32 * Side effects: overwrites r7, r8
39 b 2f
45 bne 2b
51 * Side effects: overwrites r7
56 beq 1b
62 * Side effects: overwrites r7
[all …]
|
| /linux/arch/x86/kernel/acpi/ |
| H A D | boot.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * boot.c - Architecture-Specific Low-Level ACPI Boot Support
22 #include <linux/efi-bgrt.h>
75 * Hotplug side:
76 * ->device_hotplug_lock
77 * ->acpi_ioapic_lock
78 * ->ioapic_lock
79 * Interrupt mapping side:
80 * ->acpi_ioapic_lock
81 * ->ioapic_mutex
[all …]
|
| /linux/include/linux/ |
| H A D | rcupdate.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Read-Copy Update mechanism for mutual exclusion
15 * For detailed explanation of Read-Copy Update mechanism see -
31 #include <asm/processor.h>
34 #define ULONG_CMP_GE(a, b) (ULONG_MAX / 2 >= (a) - (b)) argument
35 #define ULONG_CMP_LT(a, b) (ULONG_MAX / 2 < (a) - (b)) argument
38 #define RCU_SEQ_STATE_MASK ((1 << RCU_SEQ_CTR_SHIFT) - 1)
50 // not-yet-completed RCU grace periods.
54 * same_state_synchronize_rcu - Are two old-state values identical?
55 * @oldstate1: First old-state value.
[all …]
|
| /linux/arch/powerpc/platforms/powermac/ |
| H A D | udbg_scc.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2001-2005 PPC 64 Team, IBM Corp
10 #include <asm/processor.h>
40 return -1; in udbg_scc_getc_poll()
42 return -1; in udbg_scc_getc_poll()
52 return -1; in udbg_scc_getc()
80 path = of_get_property(of_chosen, "linux,stdout-path", NULL); in udbg_scc_init()
88 if (of_node_name_eq(ch, "ch-a")) { in udbg_scc_init()
98 /* Get address within mac-io ASIC */ in udbg_scc_init()
104 /* Get address of mac-io PCI itself */ in udbg_scc_init()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen3/ |
| H A D | memory.json | 5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St…
6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older …
24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
36 … "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event."
46 …"BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and…
84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.",
91 …esses, although these are generally rare. Each increment represents an eight-byte access, although…
258 "BriefDescription": "Total Page Table Walks on I-side.",
276 "BriefDescription": "Total Page Table Walks on D-side.",
300 "BriefDescription": "The number of 64B misaligned (i.e., cacheline crossing) loads.",
[all …]
|
| /linux/Documentation/arch/powerpc/ |
| H A D | transactional_memory.rst | 36 b continue
43 b begin_move_money
47 Between these points the processor is in 'Transactional' state; any memory
49 transactional or non-transactional accesses within the system. In this
50 example, the transaction completes as though it were normal straight-line code
51 IF no other processor has touched SAVINGS_ACCT(r3) or CURRENT_ACCT(r3); an
69 - Conflicts with cache lines used by other processors
70 - Signals
71 - Context switches
72 - See the ISA for full documentation of everything that will abort transactions.
[all …]
|
| /linux/drivers/net/wireless/intel/iwlegacy/ |
| H A D | csr.h | 8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
70 * low power states due to driver-invoked device resets
71 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
77 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
100 * 31-8: Reserved
101 * 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
102 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
[all …]
|
| /linux/arch/sparc/include/asm/ |
| H A D | oplib_64.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
85 /* Enter the prom, with no chance of continuation for the stand-alone
90 /* Halt and power-off the machine. */
153 /* Load explicit I/D TLB entries into the calling processor. */
166 #define PROM_MAP_READ 0x0002 /* Readable - sw */
167 #define PROM_MAP_EXEC 0x0004 /* Executable - sw */
170 #define PROM_MAP_SE 0x0040 /* Side-Effects */
172 #define PROM_MAP_IE 0x0100 /* Invert-Endianness */
191 * Returns -1 on error (ie. no such property at this node).
196 * the number of bytes the prom put into your buffer or -1 on error.
[all …]
|
| /linux/arch/mips/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
144 bool "Generic board-agnostic MIPS kernel"
201 bool "Alchemy processor based machines"
286 Build a generic DT-based kernel image that boots on select
287 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
379 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
380 DECstation porting pages on <http://decstation.unix-ag.org/>.
444 Olivetti M700-10 workstations.
481 bool "Loongson 32-bit family of machines"
501 This enables support for the Loongson-1 family of machines.
[all …]
|
| /linux/Documentation/arch/sparc/oradax/ |
| H A D | dax-hv-api.txt | 3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
82 … "ORCL,sun4v-dax-fc" is compatible with the "ORCL,sun4v-dax" interface, and includes additional CCB
[all …]
|
| /linux/arch/xtensa/variants/csp/include/variant/ |
| H A D | core.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3 * processor CORE configuration
8 /* Xtensa processor core configuration information.
10 Copyright (c) 1999-2015 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
[all …]
|
| /linux/arch/xtensa/variants/test_kc705_be/include/variant/ |
| H A D | core.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3 * processor CORE configuration
8 /* Xtensa processor core configuration information.
10 Copyright (c) 1999-2015 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 1 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
[all …]
|
| /linux/arch/xtensa/variants/test_kc705_hifi/include/variant/ |
| H A D | core.h | 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
3 * processor CORE configuration
8 /* Xtensa processor core configuration information.
10 Copyright (c) 1999-2014 Tensilica Inc.
45 /*----------------------------------------------------------------------
47 ----------------------------------------------------------------------*/
49 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
55 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
56 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
57 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
[all …]
|
| /linux/Documentation/gpu/ |
| H A D | komeda-kms.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 The drm/komeda driver supports the Arm display processor D71 and later products,
23 -----
30 ------
39 -------------------
41 frame. its output frame can be fed into post image processor for showing it on
47 --------------------------
51 Post image processor (improc)
52 -----------------------------
53 Post image processor adjusts frame data like gamma and color space to fit the
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/haswellx/ |
| H A D | uncore-interconnect.json | 111 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
116 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
121 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
126 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
131 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
136 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
141 "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
146 "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
151 "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
156 "PublicDescription": "Counts Timeouts - Se
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/broadwellx/ |
| H A D | uncore-interconnect.json | 111 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic Transactions as Secondary",
116 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Atomic Transactions as Secondary",
121 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Transactions as Secondary",
126 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Read Transactions as Secondary",
131 "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write Transactions as Secondary",
136 "PublicDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
141 "BriefDescription": "Misc Events - Set 0; Fastpath Rejects",
146 "PublicDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
151 "BriefDescription": "Misc Events - Set 0; Fastpath Requests",
156 "PublicDescription": "Counts Timeouts - Se
[all...] |
| /linux/drivers/slimbus/ |
| H A D | slimbus.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2011-2017, The Linux Foundation
38 #define SLIM_HEADER_GET_MT(b) ((b >> SLIM_MSG_MT_SHIFT) & SLIM_MSG_MT_MASK) argument
39 #define SLIM_HEADER_GET_RL(b) ((b >> SLIM_MSG_RL_SHIFT) & SLIM_MSG_RL_MASK) argument
40 #define SLIM_HEADER_GET_MC(b) ((b >> SLIM_MSG_MC_SHIFT) & SLIM_MSG_MC_MASK) argument
41 #define SLIM_HEADER_GET_DT(b) ((b >> SLIM_MSG_DT_SHIFT) & SLIM_MSG_DT_MASK) argument
91 * struct slim_framer - Represents SLIMbus framer.
94 * Manager is responsible for framer hand-over.
111 * struct slim_msg_txn - Message to be sent by the controller.
120 * (relevant for message-codes involving read operation)
[all …]
|