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/linux/Documentation/devicetree/bindings/powerpc/
H A Dibm,powerpc-cpu-features.txt13 enablement, privilege, and compatibility metadata.
94 - usable-privilege
104 This property describes the privilege levels and/or software components
118 This property describes the HV privilege support required to enable the
119 feature to lesser privilege levels. If the property does not exist then no
137 This property describes the OS privilege support required to enable the
138 feature to lesser privilege levels. If the property does not exist then no
179 This property may exist when the usable-privilege property value has PR bit set.
213 usable-privilege = <1 | 2 | 4>;
219 usable-privilege = <1 | 2>;
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/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts46 usable-privilege = <6>;
52 usable-privilege = <7>;
59 usable-privilege = <6>;
65 usable-privilege = <7>;
70 usable-privilege = <2>;
78 usable-privilege = <7>;
87 usable-privilege = <7>;
96 usable-privilege = <7>;
104 usable-privilege = <7>;
109 usable-privilege = <7>;
/linux/arch/arm64/include/asm/
H A Dhw_breakpoint.h17 privilege : 2, member
27 /* Privilege Levels */
35 u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) | in encode_ctrl_reg()
38 if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1) in encode_ctrl_reg()
49 ctrl->privilege = reg & 0x3; in decode_ctrl_reg()
/linux/arch/arm64/kernel/
H A Dhw_breakpoint.c139 * Convert a breakpoint privilege level to the corresponding exception
142 static enum dbg_active_el debug_exception_level(int privilege) in debug_exception_level() argument
144 switch (privilege) { in debug_exception_level()
150 pr_warn("invalid breakpoint privilege level %d\n", privilege); in debug_exception_level()
231 enum dbg_active_el dbg_el = debug_exception_level(info->ctrl.privilege); in hw_breakpoint_control()
491 * Privilege in arch_build_bp_info()
496 hw->ctrl.privilege = AARCH64_BREAKPOINT_EL1; in arch_build_bp_info()
498 hw->ctrl.privilege = AARCH64_BREAKPOINT_EL0; in arch_build_bp_info()
571 if (hw->ctrl.privilege == AARCH64_BREAKPOINT_EL1 && bp->hw.target) in hw_breakpoint_arch_parse()
584 int i, max_slots, privilege; in toggle_bp_registers() local
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/linux/arch/arm/include/asm/
H A Dhw_breakpoint.h17 privilege : 2,
31 (ctrl.privilege << 1) | ctrl.enabled; in encode_ctrl_reg()
39 ctrl->privilege = reg & 0x3; in decode_ctrl_reg()
68 /* Privilege Levels */
/linux/arch/sparc/include/uapi/asm/
H A Dpsr.h7 * PSTATE.PRIV for the current CPU privilege level.
24 #define PSR_PS 0x00000040 /* previous privilege level */
25 #define PSR_S 0x00000080 /* current privilege level */
H A Dpsrcompat.h10 #define PSR_PS 0x00000040 /* previous privilege level */
11 #define PSR_S 0x00000080 /* current privilege level */
/linux/include/linux/
H A Dtsm.h13 * Privilege level is a nested permission concept to allow confidential
20 * @privlevel: optional privilege level to associate with @outblob
60 * @TSM_REPORT_PRIVLEVEL: index of the desired privilege level attribute
/linux/Documentation/gpu/nova/core/
H A Ddevinit.rst57 The initialization process involves careful privilege management. For example, before
58 accessing certain completion status registers, the driver must check privilege level
60 privilege level to allow CPU (LS/low-secure) access. This is the case, for example,
/linux/Documentation/userspace-api/
H A Dno_new_privs.rst26 promises not to grant the privilege to do anything that could not have
41 Note that ``no_new_privs`` does not prevent privilege changes that do not
/linux/Documentation/devicetree/bindings/bus/
H A Dst,stm32mp25-rifsc.yaml21 any security domains (secure, privilege, compartment).
30 security domains (secure, privilege, compartment).
/linux/drivers/perf/
H A DKconfig105 full perf feature support i.e. counter overflow, privilege mode
233 branch types and privilege based filtering. It captures additional
235 type, branch privilege level etc.
H A Darm_brbe.c368 * BRBE supports the following privilege mode filters while generating
408 * captured, irrespective of the perf event's privilege. in branch_type_to_brbcr()
409 * If the perf event does not have enough privilege for in branch_type_to_brbcr()
592 pr_warn_once("%d - unknown branch privilege captured\n", brbe_el); in brbinf_get_perf_priv()
641 * Branch privilege level is available for target only and complete in perf_entry_from_brbe_regset()
/linux/drivers/gpu/nova-core/
H A Dgfw.rs47 // (FWSEC) lowers the privilege level to allow CPU (LS/Light-secured) access. We can only in wait_gfw_boot_completion()
49 // that the privilege level has been lowered. in wait_gfw_boot_completion()
H A Dregs.rs119 // Privilege level mask register. It dictates whether the host CPU has privilege to access the
122 "Privilege level mask register" {
/linux/tools/perf/arch/x86/util/
H A Devsel.c118 return scnprintf(msg, size, "AMD IBS doesn't support privilege filtering. Try " in arch_evsel__open_strerror()
119 "again without the privilege modifiers (like 'k') at the end."); in arch_evsel__open_strerror()
/linux/Documentation/admin-guide/LSM/
H A DSmack.rst425 Privilege:
427 policy is said to have privilege. As of this writing a task can
428 have privilege either by possessing capabilities or by having an
614 only be changed by a process with privilege.
616 Privilege section in Smack Basics
779 privilege.
793 program has appropriate privilege::
798 packets will be checked if the program has appropriate privilege.
/linux/tools/testing/selftests/powerpc/dscr/
H A Ddscr_explicit_test.c7 * privilege state SPR and the problem state SPR for this purpose.
9 * When using the privilege state SPR, the instructions such as
/linux/Documentation/arch/powerpc/
H A Dultravisor.rst26 | Privilege States |
68 * The privilege of a process is now determined by three MSR bits,
70 from least privilege to highest privilege. The higher privilege
71 modes can access all the resources of the lower privilege modes.
76 | S | HV| PR|Privilege |
90 | S | HV| PR|Privilege |
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dsifive,plic-1.0.0.yaml17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
/linux/Documentation/ABI/testing/
H A Dconfigfs-tsm-report83 different privilege levels, like SEV-SNP "VMPL", specify the
84 privilege level via this attribute. The minimum acceptable
/linux/Documentation/translations/zh_CN/security/
H A Dcredentials.rst202 * UNIX exec privilege escalation bits (SUID/SGID);
203 * File capabilities exec privilege escalation bits.
/linux/security/
H A Dcommoncap.c39 * to get full privilege on a kernel without file capabilities
341 * Erase the privilege-enhancing security markings on an inode.
810 * @effective: Do we have effective root privilege?
989 /* Check for privilege-elevated exec. */ in cap_bprm_creds_from_file()
1105 * of its privilege. The call to setuid(!=0) would drop all privileges!
1308 * system from legacy UID=0 based privilege (when filesystem in cap_task_prctl()
1323 * capability-based-privilege environment. in cap_task_prctl()
1340 * Doing anything requires privilege (go read about the in cap_task_prctl()
/linux/arch/arm/kernel/
H A Dhw_breakpoint.c570 /* Privilege */ in arch_build_bp_info()
571 hw->ctrl.privilege = ARM_BREAKPOINT_USER; in arch_build_bp_info()
573 hw->ctrl.privilege |= ARM_BREAKPOINT_PRIV; in arch_build_bp_info()
674 info->step_ctrl.privilege = info->ctrl.privilege; in enable_single_step()
724 return !user_mode(regs) && info->ctrl.privilege == ARM_BREAKPOINT_USER; in watchpoint_fault_on_uaccess()
/linux/Documentation/security/
H A Dcredentials.rst238 * UNIX exec privilege escalation bits (SUID/SGID);
239 * File capabilities exec privilege escalation bits.
243 privilege escalation bits come into play, and may allow the resulting process
545 To avoid "confused deputy" privilege escalation attacks, access control checks

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