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/linux/drivers/mfd/
H A Dwm8350-irq.c35 int primary; member
43 .primary = WM8350_OC_INT,
49 .primary = WM8350_UV_INT,
54 .primary = WM8350_UV_INT,
59 .primary = WM8350_UV_INT,
64 .primary = WM8350_UV_INT,
69 .primary = WM8350_UV_INT,
74 .primary = WM8350_UV_INT,
79 .primary = WM8350_UV_INT,
84 .primary = WM8350_UV_INT,
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/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dsd.h11 struct mlx5_core_dev *mlx5_sd_primary_get_peer(struct mlx5_core_dev *primary, int idx);
14 struct mlx5_core_dev *mlx5_sd_ch_ix_get_dev(struct mlx5_core_dev *primary, int ch_ix);
22 #define mlx5_sd_for_each_dev_from_to(i, primary, ix_from, to, pos) \ argument
24 (pos = mlx5_sd_primary_get_peer(primary, i)) && pos != (to); i++)
26 #define mlx5_sd_for_each_dev(i, primary, pos) \ argument
27 mlx5_sd_for_each_dev_from_to(i, primary, 0, NULL, pos)
29 #define mlx5_sd_for_each_dev_to(i, primary, to, pos) \ argument
30 mlx5_sd_for_each_dev_from_to(i, primary, 0, to, pos)
32 #define mlx5_sd_for_each_secondary(i, primary, pos) \ argument
33 mlx5_sd_for_each_dev_from_to(i, primary, 1, NULL, pos)
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/linux/Documentation/virt/
H A Dne_overview.rst16 application then runs in a separate VM than the primary VM, namely an enclave.
24 carved out of the primary VM. Each enclave is mapped to a process running in the
25 primary VM, that communicates with the NE kernel driver via an ioctl interface.
29 1. An enclave abstraction process - a user space process running in the primary
33 There is a NE emulated PCI device exposed to the primary VM. The driver for this
39 hypervisor running on the host where the primary VM is running. The Nitro
42 2. The enclave itself - a VM running on the same host as the primary VM that
43 spawned it. Memory and CPUs are carved out of the primary VM and are dedicated
46 The memory regions carved out of the primary VM and given to an enclave need to
53 available for the primary VM. A CPU pool has to be set for NE purposes by an
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/linux/sound/soc/sof/
H A Dipc4.c190 val = msg->primary & SOF_IPC4_MSG_TARGET_MASK; in sof_ipc4_log_header()
191 type = SOF_IPC4_MSG_TYPE_GET(msg->primary); in sof_ipc4_log_header()
208 u32 notif = SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary); in sof_ipc4_log_header()
225 text, msg->primary, msg->extension, str, str2, in sof_ipc4_log_header()
228 dev_dbg(dev, "%s: %#x|%#x: %s|%s\n", text, msg->primary, in sof_ipc4_log_header()
233 text, msg->primary, msg->extension, str, in sof_ipc4_log_header()
236 dev_dbg(dev, "%s: %#x|%#x: %s\n", text, msg->primary, in sof_ipc4_log_header()
266 !SOF_IPC4_MSG_IS_MODULE_MSG(msg->primary) && in sof_ipc4_log_header()
267 SOF_IPC4_MSG_TYPE_GET(msg->primary) == SOF_IPC4_GLB_NOTIFICATION && in sof_ipc4_log_header()
268 SOF_IPC4_NOTIFICATION_TYPE_GET(msg->primary) == SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS) in sof_ipc4_log_header()
[all …]
H A Dsof-client-probes-ipc4.c151 msg.primary = mentry->id; in ipc4_probes_deinit()
152 msg.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_INIT_INSTANCE); in ipc4_probes_deinit()
153 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST); in ipc4_probes_deinit()
154 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG); in ipc4_probes_deinit()
182 msg.primary = mentry->id; in ipc4_probes_points_info()
183 msg.primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_MOD_DELETE_INSTANCE); in ipc4_probes_points_info()
184 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
185 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_MODULE_MSG);
234 msg.primary = mentry->id; in ipc4_probes_points_add()
235 msg.primary | in ipc4_probes_points_add()
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H A Dipc4-pcm.c81 u32 primary, ipc_size; in sof_ipc4_set_multi_pipeline_state() local
94 primary = state; in sof_ipc4_set_multi_pipeline_state()
95 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE); in sof_ipc4_set_multi_pipeline_state()
96 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST); in sof_ipc4_set_multi_pipeline_state()
97 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG); in sof_ipc4_set_multi_pipeline_state()
98 msg.primary = primary; in sof_ipc4_set_multi_pipeline_state()
114 u32 primary; in sof_ipc4_set_pipeline_state() local
119 primary = state; in sof_ipc4_set_pipeline_state()
120 primary | in sof_ipc4_set_pipeline_state()
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/linux/drivers/gpu/drm/v3d/
H A Dv3d_trace.h26 __entry->dev = dev->primary->index;
52 __entry->dev = dev->primary->index;
78 __entry->dev = dev->primary->index;
98 __entry->dev = dev->primary->index;
118 __entry->dev = dev->primary->index;
138 __entry->dev = dev->primary->index;
157 __entry->dev = dev->primary->index;
177 __entry->dev = dev->primary->index;
197 __entry->dev = dev->primary->index;
219 __entry->dev = dev->primary->index;
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/linux/drivers/gpu/drm/
H A Ddrm_modeset_helper.c107 * creating the primary plane.
124 * Initialize a CRTC object with a default helper-provided primary plane and no
130 * 1. Primary plane cannot be repositioned.
131 * 2. Primary plane cannot be scaled.
132 * 3. Primary plane must cover the entire CRTC.
134 * 5. The primary plane must always be on if the CRTC is enabled.
137 * should instead implement their own primary plane. Atomic drivers must do so.
148 struct drm_plane *primary; in drm_crtc_init() local
152 primary = __drm_universal_plane_alloc(dev, sizeof(*primary), 0, 0, in drm_crtc_init()
157 if (IS_ERR(primary)) in drm_crtc_init()
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/linux/Documentation/security/tpm/
H A Dtpm-security.rst88 The mechanism chosen for the Linux Kernel is to derive the primary
102 certifying the null seed primary with that key) which is too complex
103 to run within the kernel, so we keep a copy of the null primary key
106 that if the null primary key certifies correctly, you know all your
114 In the current null primary scenario, the TPM must be completely
137 kernel must be created using the null primary key as the salt key
139 derivation. Thus, the kernel creates the null primary key once (as a
150 For every in-kernel operation we use null primary salted HMAC to
155 Null Primary Key Certification in Userspace
159 primary endorsement key. This document assumes that the Elliptic
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/linux/Documentation/arch/sparc/oradax/
H A Ddax-hv-api.txt162 0b'11 Primary context virtual address
167 0b'011 Primary context virtual address
183 0b'011 Primary context virtual address
188 [4:2] Primary source address type
192 0b'011 Primary context virtual address
201 0b'11 Primary context virtual address
247 …require multiple data streams for processing, requiring the specification of both primary data for…
250 36.2.1.1.1. Primary Input Format
252 …The primary input format code is a 4-bit field when it is used. There are 10 primary input formats…
301 36.2.1.1.2. Primary Input Element Size
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/linux/arch/sparc/include/uapi/asm/
H A Dasi.h129 #define ASI_AIUP 0x10 /* Primary, user */
131 #define ASI_AIUPL 0x18 /* Primary, user, little endian */
133 #define ASI_P 0x80 /* Primary, implicit */
135 #define ASI_PNF 0x82 /* Primary, no fault */
137 #define ASI_PL 0x88 /* Primary, implicit, l-endian */
139 #define ASI_PNFL 0x8a /* Primary, no fault, l-endian */
230 #define ASI_BLK_AIUP 0x70 /* Primary, user, block load/store */
241 #define ASI_BLK_AIUPL 0x78 /* Primary, user, little, blk ld/st*/
252 0x92 /* (NG7) MCD store BLKINIT primary */
254 #define ASI_PST8_P 0xc0 /* Primary, 8 8-bit, partial */
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-colorimetry.rst65 primary component c of the mastering display in increments of 0.00002.
68 primary, c equal to 1 corresponds to Blue primary and c equal to 2
69 corresponds to the Red color primary.
73 primary component c of the mastering display in increments of 0.00002.
76 primary, c equal to 1 corresponds to Blue primary and c equal to 2
77 corresponds to Red color primary.
/linux/Documentation/gpu/amdgpu/display/
H A Dmpo-overview.rst31 * ``DRM_PLANE_TYPE_PRIMARY``: Primary planes represent a "main" plane for a
32 CRTC, primary planes are the planes operated upon by CRTC modesetting and
36 * ``DRM_PLANE_TYPE_OVERLAY``: Overlay planes represent all non-primary,
43 * 4 Primary planes (1 per CRTC).
55 A typical MPO configuration from userspace - 1 primary + 1 overlay on a single
58 At least 1 pipe must be used per plane (primary and overlay), so for this
80 * Only primary planes have color-space and non-RGB format support
111 Video playback should be done using the "primary plane as underlay" MPO
114 * 1 YUV DRM Primary Plane (e.g. NV12 Video)
118 - Primary plane contains one or more videos
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/linux/drivers/gpu/drm/fsl-dcu/
H A Dfsl_dcu_drm_plane.c208 struct drm_plane *primary; in fsl_dcu_drm_primary_create_plane() local
211 primary = kzalloc(sizeof(*primary), GFP_KERNEL); in fsl_dcu_drm_primary_create_plane()
212 if (!primary) { in fsl_dcu_drm_primary_create_plane()
213 DRM_DEBUG_KMS("Failed to allocate primary plane\n"); in fsl_dcu_drm_primary_create_plane()
218 ret = drm_universal_plane_init(dev, primary, 0, in fsl_dcu_drm_primary_create_plane()
224 kfree(primary); in fsl_dcu_drm_primary_create_plane()
225 primary = NULL; in fsl_dcu_drm_primary_create_plane()
227 drm_plane_helper_add(primary, &fsl_dcu_drm_plane_helper_funcs); in fsl_dcu_drm_primary_create_plane()
229 return primary; in fsl_dcu_drm_primary_create_plane()
H A Dfsl_dcu_drm_crtc.c172 struct drm_plane *primary; in fsl_dcu_drm_crtc_create() local
178 primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm); in fsl_dcu_drm_crtc_create()
179 if (!primary) in fsl_dcu_drm_crtc_create()
182 ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL, in fsl_dcu_drm_crtc_create()
185 primary->funcs->destroy(primary); in fsl_dcu_drm_crtc_create()
/linux/sound/soc/qcom/qdsp6/
H A Dq6dsp-lpass-ports.c352 .stream_name = "Primary MI2S Playback",
366 .stream_name = "Primary MI2S Capture",
487 Q6AFE_TDM_PB_DAI("Primary", 0, PRIMARY_TDM_RX_0),
488 Q6AFE_TDM_PB_DAI("Primary", 1, PRIMARY_TDM_RX_1),
489 Q6AFE_TDM_PB_DAI("Primary", 2, PRIMARY_TDM_RX_2),
490 Q6AFE_TDM_PB_DAI("Primary", 3, PRIMARY_TDM_RX_3),
491 Q6AFE_TDM_PB_DAI("Primary", 4, PRIMARY_TDM_RX_4),
492 Q6AFE_TDM_PB_DAI("Primary", 5, PRIMARY_TDM_RX_5),
493 Q6AFE_TDM_PB_DAI("Primary", 6, PRIMARY_TDM_RX_6),
494 Q6AFE_TDM_PB_DAI("Primary", 7, PRIMARY_TDM_RX_7),
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/linux/drivers/mtd/chips/
H A Dgen_probe.c35 mtd = check_cmd_set(map, 1); /* First the primary cmdset */ in mtd_do_chip_probe()
199 int primary) in cfi_cmdset_unknown() argument
202 __u16 type = primary?cfi->cfiq->P_ID:cfi->cfiq->A_ID; in cfi_cmdset_unknown()
221 mtd = (*probe_function)(map, primary); in cfi_cmdset_unknown()
232 static struct mtd_info *check_cmd_set(struct map_info *map, int primary) in check_cmd_set() argument
235 __u16 type = primary?cfi->cfiq->P_ID:cfi->cfiq->A_ID; in check_cmd_set()
247 return cfi_cmdset_0001(map, primary); in check_cmd_set()
253 return cfi_cmdset_0002(map, primary); in check_cmd_set()
257 return cfi_cmdset_0020(map, primary); in check_cmd_set()
260 return cfi_cmdset_unknown(map, primary); in check_cmd_set()
/linux/Documentation/admin-guide/blockdev/drbd/
H A Dpeer-states-8.dot2 Secondary -> Primary [ label = "recv state packet" ]
3 Primary -> Secondary [ label = "recv state packet" ]
4 Primary -> Unknown [ label = "connection lost" ]
6 Unknown -> Primary [ label = "connected" ]
/linux/arch/powerpc/kvm/
H A Dbook3s_hv_ras.c126 * be handled by the primary thread in virtual mode. We can't in kvmppc_realmode_machine_check()
241 * kvmppc_realmode_hmi_handler() is called only by primary thread during
272 * subcore status. Only primary threads from each subcore is responsible
279 * primary threads to decide who takes up the responsibility.
282 * - Primary thread from each subcore tries to set resync required bit[63]
284 * - The first primary thread that is able to set the flag takes the
289 * - All the primary thread will clear its subcore status from subcore
291 * - Once all primary threads clear in_guest[0-3], all of them will invoke
299 * - On return of this function, primary thread will signal all
317 * By now primary thread has already completed guest->host in kvmppc_realmode_hmi_handler()
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/linux/arch/um/drivers/
H A Dchan_kern.c22 static int not_configged_open(int input, int output, int primary, void *data, in not_configged_open() argument
99 else fd = (*chan->ops->open)(chan->input, chan->output, chan->primary, in open_one_chan()
153 if (chan->primary) in open_chan()
161 if (chan && chan->primary && chan->ops->winch) in chan_enable_winch()
185 if (chan->primary) in enable_chan()
298 if (chan->primary) { in write_chan()
312 if (chan->primary) in console_write_chan()
336 if (chan && chan->primary) { in chan_window_size()
343 if (chan && chan->primary) { in chan_window_size()
361 if (chan->primary && chan->output) in free_one_chan()
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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dpamu.txt57 - fsl,primary-cache-geometry
59 Two cells that specify the geometry of the primary PAMU
107 fsl,primary-cache-geometry = <32 1>;
113 fsl,primary-cache-geometry = <32 1>;
119 fsl,primary-cache-geometry = <32 1>;
125 fsl,primary-cache-geometry = <32 1>;
131 fsl,primary-cache-geometry = <32 1>;
/linux/sound/soc/sof/intel/
H A Dhda-ipc.c77 static inline bool hda_dsp_ipc4_pm_msg(u32 primary) in hda_dsp_ipc4_pm_msg() argument
80 if (SOF_IPC4_MSG_IS_MODULE_MSG(primary) != SOF_IPC4_MODULE_MSG) in hda_dsp_ipc4_pm_msg()
83 if (SOF_IPC4_MSG_TYPE_GET(primary) == SOF_IPC4_MOD_SET_DX || in hda_dsp_ipc4_pm_msg()
84 SOF_IPC4_MSG_TYPE_GET(primary) == SOF_IPC4_MOD_SET_D0IX) in hda_dsp_ipc4_pm_msg()
96 if (hda_dsp_ipc4_pm_msg(msg_data->primary)) in hda_dsp_ipc4_schedule_d0i3_work()
123 msg_data->primary | HDA_DSP_REG_HIPCI_BUSY); in hda_dsp_ipc4_send_msg()
192 u32 primary = hipct & HDA_DSP_REG_HIPCT_MSG_MASK; in hda_dsp_ipc4_irq_thread() local
199 if (primary & SOF_IPC4_MSG_DIR_MASK) { in hda_dsp_ipc4_irq_thread()
204 data->primary = primary; in hda_dsp_ipc4_irq_thread()
211 snd_sof_ipc_reply(sdev, data->primary); in hda_dsp_ipc4_irq_thread()
[all …]
/linux/drivers/gpu/drm/vc4/
H A Dvc4_trace.h28 __entry->dev = dev->primary->index;
47 __entry->dev = dev->primary->index;
67 __entry->dev = dev->primary->index;
95 __entry->dev = dev->primary->index;
121 __entry->dev = dev->primary->index;
141 __entry->dev = dev->primary->index;
/linux/arch/sparc/kernel/
H A Dsbus.c261 #define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
262 #define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
263 #define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
288 /* Clear primary/secondary error status bits. */ in sysio_ue_handler()
297 printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n", in sysio_ue_handler()
334 #define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
335 #define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
336 #define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
362 /* Clear primary/secondary error status bits. */ in sysio_ce_handler()
370 printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n", in sysio_ce_handler()
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/linux/tools/perf/scripts/python/
H A Dexport-to-sqlite.py166 'id integer NOT NULL PRIMARY KEY,'
169 'id integer NOT NULL PRIMARY KEY,'
173 'id integer NOT NULL PRIMARY KEY,'
179 'id integer NOT NULL PRIMARY KEY,'
185 'id integer NOT NULL PRIMARY KEY,'
189 'id integer NOT NULL PRIMARY KEY,'
195 'id integer NOT NULL PRIMARY KEY,'
202 'id integer NOT NULL PRIMARY KEY,'
207 'id integer NOT NULL PRIMARY KEY,'
230 'id integer NOT NULL PRIMARY KEY,'
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