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/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhxge_tdc_hw.h77 * the PCI-E bus. Fields in this register are part of the dma
78 * configuration and cannot be changed once the dma is enabled.
80 * Page handle, bits [63:44] of all PCI-E transactions for this
102 * Description: Configuration parameters for transmit DMA block.
105 * part of the dma configuration and cannot be changed once the dma
110 * should use the following sequence to reset a DMA channel. First,
111 * set DMA.enable to 0, wait for DMA.qst=1 and then, set DMA.reset to
112 * 1. After DMA.reset is cleared by hardware and the DMA.qst is set
113 * to 1, software may then start configuring the DMA channel. The
114 * DMA.enable can be set or cleared while the DMA is in operation.
[all …]
H A Dhxge_rdc_hw.h83 * Description: Logical page handle specifying upper bits of 64-bit
84 * PCIE addresses. Fields in this register are part of the dma
85 * configuration and cannot be changed once the dma is enabled.
87 * Bits [63:44] of a 64-bit address, used to concatenate to a
88 * 44-bit address when generating 64-bit addresses on the PCIE
109 * DMA Configuration 1
110 * Description: Configuration parameters for receive DMA block.
111 * Fields in this register are part of the dma configuration and
112 * cannot be changed once the dma is enabled.
114 * should use the following sequence to reset a DMA channel. First,
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H A Dhxge_rxdma.c32 * Number of blocks to accumulate before re-enabling DMA
118 hxgep->rdc_first_intr[i] = B_TRUE; in hxge_init_rxdma_channels()
123 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); in hxge_init_rxdma_channels()
198 rdc_desc.mbox_addr = mbox_p->mbox_addr; in hxge_enable_rxdma_channel()
201 mbox_p->mbox_addr, rdc_desc.mbox_addr)); in hxge_enable_rxdma_channel()
203 rdc_desc.rbr_len = rbr_p->rbb_max; in hxge_enable_rxdma_channel()
204 rdc_desc.rbr_addr = rbr_p->rbr_addr; in hxge_enable_rxdma_channel()
206 switch (hxgep->rx_bksize_code) { in hxge_enable_rxdma_channel()
215 rdc_desc.size0 = rbr_p->hpi_pkt_buf_size0; in hxge_enable_rxdma_channel()
218 rdc_desc.size1 = rbr_p->hpi_pkt_buf_size1; in hxge_enable_rxdma_channel()
[all …]
/illumos-gate/usr/src/uts/common/io/comstar/port/qlt/
H A Dqlt_dma.c23 * Copyright 2009-2015 QLogic Corporation. All rights reserved.
70 0, /* low DMA address range */
71 0xffffffffffffffff, /* high DMA address range */
72 0xffffffff, /* DMA counter register */
73 8192, /* DMA address alignment */
74 0xff, /* DMA burstsizes */
75 1, /* min effective DMA size */
76 0xffffffff, /* max DMA xfer size */
80 0 /* DMA transfer flags */
99 if (qlt->qlt_bucketcnt[0] != 0) { in qlt_dmem_init()
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/illumos-gate/usr/src/man/man9s/
H A Dddi_dmae_req.9s9 ddi_dmae_req \- DMA engine request structure
19 parameters for a \fBDMA\fR channel. This structure contains all the information
20 necessary to set up the channel, except for the \fBDMA\fR memory address and
23 performance. The \fBDMA\fR engine request structure is passed to
27 controls some aspect of DMA engine operation. The structure members associated
28 with supported DMA engine options are described here.
48 Specifies what \fBDMA\fR operation is to be performed. The value
62 \fBDMAE_BUF_CHAIN\fR to specify that multiple \fBDMA\fR cookies will be given
63 to the \fBDMA\fR engine for a single \fBI/O\fR transfer. This action causes a
65 \fBddi_dmae_prog()\fR to give the \fBDMA\fR engine the \fBDMA\fR engine request
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/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_rxdma.h207 * rdc: RX DMA Channel number
280 * Enable PIO access to shadow and prefetch memory.
281 * In the case of DMA errors, software may need to
282 * initialize the shadow and prefetch memories to
283 * sane value (may be clear it) before re-enabling
284 * the DMA channel.
301 * Disable PIO access to shadow and prefetch memory.
320 * This determines the granularity of RX DMA countdown timers
384 * rdc: RX DMA Channel number
457 * rdc: RX DMA Channel number
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H A Dnpi_rxdma.c123 * rdc: RX DMA number
275 ASSERT(RXDMA_PAGE_VALID(pg_cfg->page_num)); in npi_rxdma_cfg_logical_page()
276 if (!RXDMA_PAGE_VALID(pg_cfg->page_num)) { in npi_rxdma_cfg_logical_page()
280 pg_cfg->page_num)); in npi_rxdma_cfg_logical_page()
287 if (!pg_cfg->valid) { in npi_rxdma_cfg_logical_page()
288 if (pg_cfg->page_num == 0) in npi_rxdma_cfg_logical_page()
291 if (pg_cfg->page_num == 1) in npi_rxdma_cfg_logical_page()
297 if (pg_cfg->page_num == 0) { in npi_rxdma_cfg_logical_page()
304 if (pg_cfg->page_num == 1) { in npi_rxdma_cfg_logical_page()
312 page_vld.bits.ldw.func = pg_cfg->func_num; in npi_rxdma_cfg_logical_page()
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/illumos-gate/usr/src/uts/common/io/i40e/
H A Di40e_osdep.h84 #define FIELD_SIZEOF(x, y) (sizeof (((x*)0)->y))
117 * Note, while prefetch is strictly not present on all architectures, (it's an
120 #define prefetch(x) prefetch_read_many(x) macro
144 u64 pa; /* Physical (DMA/Hardware) address. */
147 /* illumos-private members */
149 ddi_dma_handle_t idm_dma_handle; /* DMA handle */
155 #define OS_DEP(hw) ((struct i40e_osdep *)((hw)->back))
157 (pci_config_get16(OS_DEP(hw)->ios_cfg_handle, (reg)))
159 (pci_config_put16(OS_DEP(hw)->ios_cfg_handle, (reg), (value)))
163 * read and write the 32-bit register in PCI space.
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/illumos-gate/usr/src/uts/sun4u/sys/pci/
H A Dpci_simba.h23 * Copyright (c) 1994-1998 by Sun Microsystems, Inc.
50 #define PCI_BCNF_DMA_AFSR 0xc8 /* dma afsr */
51 #define PCI_BCNF_DMA_AFAR 0xd0 /* dma afar */
54 #define PCI_BCNF_DMATGT_RTY_LIMIT 0xda /* dma target retry limit */
55 #define PCI_BCNF_DMATGT_LATE_TIMER 0xdb /* dma target retry limit */
63 #define PCI_BCNF_CTL_STAT 0xe0 /* control-status */
89 #define PCI_SEC_CNTL_PIO_PREF 0x1 /* prefetch dma reads as pio */
134 #define PCI_DIAG_IDMA_WDATA_PAR 0x1 /* invert dma wr data parity */
135 #define PCI_DIAG_IDMA_RDATA_PAR 0x2 /* invert dma rd data parity */
136 #define PCI_DIAG_IDMA_ADDR_PAR 0x4 /* invert dma addr parity */
H A Dpcisch.h40 * Schizo-specific register offsets & bit field positions.
45 * 0x00 <chip_type> <version#> <module-revision#>
162 * MAX_PRF when enabled will always prefetch the max of 8
189 * Schizo-specific fields of interrupt mapping register:
331 #define SCHIZO_VPN_MASK ((1 << 19) - 1)
379 * XMITS PCI-X Diagnostic Register bit definitions
393 * XMITS PCI-X Error Status Register bit definitions
403 * As a workaround for an XMITS ASIC bug, the following PCI-X errors are
404 * assigned new bit positions within the PCI-X Error Status Register to
409 * -------------------- ------------ ------------
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/illumos-gate/usr/src/uts/common/io/sfxge/
H A Dsfxge_ev.c2 * Copyright (c) 2008-2016 Solarflare Communications Inc.
50 /* Event queue DMA attributes */
76 efsys_mem_t *esmp = &(sep->se_mem); in _sfxge_ev_qctor()
80 /* Compile-time structure layout checks */ in _sfxge_ev_qctor()
81 EFX_STATIC_ASSERT(sizeof (sep->__se_u1.__se_s1) <= in _sfxge_ev_qctor()
82 sizeof (sep->__se_u1.__se_pad)); in _sfxge_ev_qctor()
83 EFX_STATIC_ASSERT(sizeof (sep->__se_u2.__se_s2) <= in _sfxge_ev_qctor()
84 sizeof (sep->__se_u2.__se_pad)); in _sfxge_ev_qctor()
85 EFX_STATIC_ASSERT(sizeof (sep->__se_u3.__se_s3) <= in _sfxge_ev_qctor()
86 sizeof (sep->__se_u3.__se_pad)); in _sfxge_ev_qctor()
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H A Dsfxge_rx.c2 * Copyright (c) 2008-2016 Solarflare Communications Inc.
66 /* Receive packet DMA attributes */
89 /* Receive queue DMA attributes */
120 dev_info_t *dip = sp->s_dip; in sfxge_rx_packet_ctor()
123 ASSERT3U(sizeof (srpp->__srp_u1.__srp_s1), <=, in sfxge_rx_packet_ctor()
124 sizeof (srpp->__srp_u1.__srp_pad)); in sfxge_rx_packet_ctor()
125 ASSERT3U(sizeof (srpp->__srp_u2.__srp_s2), <=, in sfxge_rx_packet_ctor()
126 sizeof (srpp->__srp_u2.__srp_pad)); in sfxge_rx_packet_ctor()
130 /* Allocate a DMA handle */ in sfxge_rx_packet_ctor()
133 NULL, &(srpp->srp_dma_handle)); in sfxge_rx_packet_ctor()
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/illumos-gate/usr/src/uts/common/sys/
H A Dpci.h47 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */
182 #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */
209 #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */
229 * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
235 * PCI Sub-class codes - base class 0x1 (mass storage controllers)
245 #define PCI_MASS_NVME 0x8 /* Non-Volatile memory controller */
261 #define PCI_ATA_IF_SINGLE_DMA 0x20 /* ATA controller with single DMA */
262 #define PCI_ATA_IF_CHAINED_DMA 0x30 /* ATA controller with chained DMA */
278 * PCI Sub-class codes - base class 0x2 (Network controllers)
290 * PCI Sub-class codes - base class 03 (display controllers)
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H A Dpcic_reg.h158 * Cirrus Logic PCI-PCMCIA adapters extension register indicies
185 * Cirrus Logic PCI-PCMCIA PCIC_CLEXT_EXT_CTL_1 reg bit definitions
191 * Cirrus Logic PCI-PCMCIA PCIC_MISC_CTL_2 reg bit definitions
193 #define PCIC_CL_LP_DYN_MODE 0x02 /* low-power dynamic mode */
197 * Cirrus Logic PCI-PCMCIA PCIC_CLEXT_MISC_CTL_3 reg bit definitions
209 * Intel 82092-AA reg and bit definitions
219 #define PCIC_82092_RPFB 0x10 /* Read Prefetch Buffering */
356 /* Vadem DMA Register */
/illumos-gate/usr/src/uts/common/io/e1000g/
H A De1000g_rx.c9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
53 * e1000g_rxfree_func - the call-back function to reclaim rx buffer
69 if (packet->ref_cnt == 0) { in e1000g_rxfree_func()
77 rx_data = (e1000g_rx_data_t *)(uintptr_t)packet->rx_data; in e1000g_rxfree_func()
79 if (packet->mp == NULL) { in e1000g_rxfree_func()
83 address = (unsigned char *)packet->rx_buf->address; in e1000g_rxfree_func()
85 packet->mp = desballoc((unsigned char *) in e1000g_rxfree_func()
86 address, packet->rx_buf->size, in e1000g_rxfree_func()
87 BPRI_MED, &packet->free_rtn); in e1000g_rxfree_func()
97 mutex_enter(&rx_data->recycle_lock); in e1000g_rxfree_func()
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/illumos-gate/usr/src/uts/common/io/igc/
H A Digc_ring.c44 * DMA attributes that are used for descriptor rings. .
49 * DMA descriptor rings can show up anywhere in the address space. The
50 * card supports a 64-bit address for this.
92 * DMA attributes that cover pre-allocated data buffers. Note, RX buffers are
107 * For TX, the maximum value is a 16-bit quantity because that's the
141 * These are the DMA attributes we use when performing DMA TX binding for an
152 * For TX, the maximum value is a 16-bit quantity because that's the
188 accp->devacc_attr_version = DDI_DEVICE_ATTR_V1; in igc_dma_acc_attr()
189 accp->devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; in igc_dma_acc_attr()
190 accp->devacc_attr_dataorder = DDI_STRICTORDER_ACC; in igc_dma_acc_attr()
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/illumos-gate/usr/src/uts/common/io/yge/
H A Dyge.c16 * are provided to you under the BSD-type license terms provided
21 * - Redistributions of source code must retain the above copyright
23 * - Redistributions in binary form must reproduce the above
27 * - Neither the name of Marvell nor the names of its contributors
61 * 4. Neither the name of the author nor the names of any co-contributors
277 yge_dev_t *dev = port->p_dev; in yge_mii_readreg()
278 int pnum = port->p_port; in yge_mii_readreg()
306 yge_dev_t *dev = port->p_dev; in yge_mii_writereg()
307 int pnum = port->p_port; in yge_mii_writereg()
328 PHY_LOCK(port->p_dev); in yge_mii_read()
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H A Dyge.h12 * are provided to you under the BSD-type license terms provided
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above
23 * - Neither the name of Marvell nor the names of its contributors
57 * D-Link PCI vendor ID
91 * D-Link gigabit ethernet device ID
133 #define PCI_Y2_PIG_ENA BIT(31) /* Enable Plug-in-Go (YUKON-2) */
134 #define PCI_Y2_DLL_DIS BIT(30) /* Disable PCI DLL (YUKON-2) */
135 #define PCI_Y2_PHY2_COMA BIT(29) /* Set PHY 2 to Coma Mode (YUKON-2) */
136 #define PCI_Y2_PHY1_COMA BIT(28) /* Set PHY 1 to Coma Mode (YUKON-2) */
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/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_rxdma_hw.h37 * NIU: Receive DMA Channels
39 /* Receive DMA Clock Divider */
67 * Default Port Receive DMA Channel (RDC)
253 #define LOG_PAGE_ADDR_SHIFT 12 /* bits[43:12] --> bits[31:0] */
351 * RDC: Receive DMA Datapath Configuration
353 * each DMA channel. Each DMA CSR is 512 bytes
406 /* NOTE: offset256 valid only for Neptune-L and RF-NIU */
438 * each DMA channel.
775 * (for each DMA channel)
821 /* Receive DMA Interrupt Behavior: Event Mask (DMC + 0x00068) */
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/illumos-gate/usr/src/uts/sun/io/audio/drv/audiocs/
H A Daudio_4231.c32 * does support two different DMA engines, the APC and EB2. The code for
33 * those DMA engines is split out and a well defined, but private, interface
34 * is used to control those DMA engines.
46 * and recording. The play DMA buffers end up getting thrown away, but when
186 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, /* [000] -> [004] */
187 0x3a, 0x39, 0x38, 0x37, 0x36, /* [005] -> [009] */
188 0x35, 0x34, 0x33, 0x32, 0x31, /* [010] -> [014] */
189 0x30, 0x2f, 0x2e, 0x2d, 0x2c, /* [015] -> [019] */
190 0x2b, 0x2a, 0x29, 0x29, 0x28, /* [020] -> [024] */
191 0x28, 0x27, 0x27, 0x26, 0x26, /* [025] -> [029] */
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/illumos-gate/usr/src/uts/common/sys/sata/adapters/ahci/
H A Dahcireg.h69 #define AHCI_HBA_CAP_FBSS (0x1 << 16) /* FIS-based switching */
76 #define AHCI_HBA_CAP_SSS (0x1 << 27) /* staggered spin-up */
80 #define AHCI_HBA_CAP_S64A ((uint32_t)0x1 << 31) /* 64-bit addressing */
109 #define AHCI_HBA_EM_CTL_SUPP_SAFTE (0x1 << 17) /* SAF-TE EM Messages */
110 #define AHCI_HBA_EM_CTL_SUPP_SES2 (0x1 << 18) /* SES-2 EM Messages */
125 #define AHCI_GLOBAL_OFFSET(ahci_ctlp) (ahci_ctlp->ahcictl_ahci_addr)
151 ((0x1 << port) & ahci_ctlp->ahcictl_ports_implemented)
158 /* DMA Setup FIS Interrupt */
176 /* Interface Non-fatal Error Status */
192 #define AHCI_CMD_STATUS_SUD (0x1 << 1) /* Spin-up device */
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/illumos-gate/usr/src/uts/common/io/sfxge/common/
H A Defx_ev.c2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
40 (_eep)->ee_stat[_stat]++; \
146 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC); in efx_ev_init()
147 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR); in efx_ev_init()
149 if (enp->en_mod_flags & EFX_MOD_EV) { in efx_ev_init()
154 switch (enp->en_family) { in efx_ev_init()
179 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0); in efx_ev_init()
181 if ((rc = eevop->eevo_init(enp)) != 0) in efx_ev_init()
184 enp->en_eevop = eevop; in efx_ev_init()
185 enp->en_mod_flags |= EFX_MOD_EV; in efx_ev_init()
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/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_defines.h3 Copyright (c) 2001-2015, Intel Corporation
83 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
173 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
174 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
263 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
265 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
341 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
342 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
[all …]
/illumos-gate/usr/src/uts/common/io/igc/core/
H A Digc_defines.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
68 #define IGC_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clk Gating */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
128 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
129 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
215 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
217 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
279 /* 1000/H is not supported, nor spec-compliant. */
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/illumos-gate/usr/src/uts/intel/sys/acpi/
H A Damlresrc.h3 * Module Name: amlresrc.h - AML resource descriptors
11 * Some or all of this work - Copyright (c) 1999 - 2018, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
152 /* acpisrc:StructDefs -- for acpisrc conversion */
187 …YPE "_MEM" /* NonCache(0), Cacheable(1) Cache+combine(2), Cache+prefetch(3) */
247 #define ACPI_AML_SIZE_LARGE(r) (sizeof (r) - sizeof (AML_RESOURCE_LARGE_HEADER))
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