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/linux/Documentation/devicetree/bindings/input/
H A Dti,drv260x.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments - drv260x Haptics driver family
10 - Andrew Davis <afd@ti.com>
15 - ti,drv2604
16 - ti,drv2605
17 - ti,drv2605l
22 vbat-supply:
30 (defined in include/dt-bindings/input/ti-drv260x.h)
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/linux/Documentation/devicetree/bindings/power/supply/
H A Drichtek,rt5033-charger.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/supply/richtek,rt5033-charger.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jakob Hauser <jahau@rocketmail.com>
14 under sub-node named "charger" using the following format.
18 const: richtek,rt5033-charger
20 monitored-battery:
25 precharge-current-microamp:
26 Current of pre-charge mode. The pre-charge current levels are 350 mA
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,spmi-adc5-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-adc5-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
14 voltage. It is a 16-bit sigma-delta ADC. It also performs the same thermal
20 programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements.
26 const: qcom,spmi-adc5-gen3
30 - description: SDAM0 base address in the SPMI PMIC register map
31 - description: SDAM1 base address
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H A Dqcom,spmi-vadc-common.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
18 ADC channel number (PMIC-specific for versions after PMIC5 ADC).
34 qcom,pre-scaling:
35 $ref: /schemas/types.yaml#/definitions/uint32-array
39 pre-determined ratio and use it for post scaling. It is a pair of
45 - items:
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/linux/drivers/mtd/chips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
92 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
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/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5341.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mike Looijmans <mike.looijmans@topic.nl>
18 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
20 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
22 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
33 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
42 - silabs,si5340
43 - silabs,si5341
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/linux/Documentation/trace/coresight/
H A Dcoresight-config.rst1 .. SPDX-License-Identifier: GPL-2.0
14 programming of the CoreSight system with pre-defined configurations that
17 Many CoreSight components can be programmed in complex ways - especially ETMs.
30 --------
41 accesses in the driver - the resource usage and parameter descriptions
43 and efficient for the feature to be programmed onto the device when required.
47 will be programmed into the device hardware.
56 feature being enabled that can adjust the behaviour of the operation programmed
59 For example, this could be a count value in a programmed operation that repeats
67 system - which is described below.
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/linux/arch/powerpc/sysdev/
H A Dfsl_lbc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright © 2007-2008 MontaVista Software, Inc.
10 * Author: Roy Zang <tie-fei.zang@freescale.com>
35 * fsl_lbc_addr - convert the base address
45 struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node; in fsl_lbc_addr()
56 * fsl_lbc_find - find Localbus bank
69 if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) in fsl_lbc_find()
70 return -ENODEV; in fsl_lbc_find()
72 lbc = fsl_lbc_ctrl_dev->regs; in fsl_lbc_find()
73 for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) { in fsl_lbc_find()
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/linux/Documentation/leds/
H A Dleds-lm3556.rst6 1.5 A Synchronous Boost LED Flash Driver w/ High-Side Current Source
10 - Daniel Jeong
12 Contact:Daniel Jeong(daniel.jeong-at-ti.com, gshark.jeong-at-gmail.com)
15 -----------
50 In Torch Mode, the current source(LED) is programmed via the CURRENT CONTROL
78 and 4 patterns are pre-defined in indicator_pattern array.
80 According to N-lank, Pulse time and N Period values, different pattern wiill
84 Please refer datasheet for more detail about N-Blank, Pulse time and N Period.
118 -----
121 according to include/linux/platform_data/leds-lm3556.h, set the i2c board info
/linux/sound/oss/dmasound/
H A Ddmasound_atari.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * - added versioning
12 * - put in and populated the hardware_afmts field.
13 * [0.2] - put in SNDCTL_DSP_GETCAPS value.
14 * 01/02/2001 [0.3] - put in default hard/soft settings.
171 return -EFAULT; in ata_ct_law()
173 count--; in ata_ct_law()
192 return -EFAULT; in ata_ct_s8()
211 return -EFAULT; in ata_ct_u8()
213 count--; in ata_ct_u8()
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dmaxim,max9286.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jacopo Mondi <jacopo+renesas@jmondi.org>
12 - Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
13 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
14 - Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
18 Serial Links (GMSL) and outputs them on a CSI-2 D-PHY port using up to 4 data
28 '#address-cells':
31 '#size-cells':
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h201 * Needed to set ASIC voltages for clocks programmed by DAL
236 * Note that when setting handshake to unsupported, the call is pre-emptive. That means
238 * request to go un-acked. Only when the call completes should such a state be applied to
/linux/drivers/watchdog/
H A Dda9063_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
27 * others: timeout = 2048 ms * 2^(TWDSCALE-1).
33 #define DA9063_TWDSCALE_MAX (ARRAY_SIZE(wdt_timeout) - 1)
59 regmap_read(da9063->regmap, DA9063_REG_CONTROL_D, &val); in da9063_wdt_read_timeout()
66 return regmap_update_bits(da9063->regmap, DA9063_REG_CONTROL_D, in da9063_wdt_disable_timer()
79 * programmed because the timeout value combines two functions in da9063_wdt_update_timeout()
92 return regmap_update_bits(da9063->regmap, DA9063_REG_CONTROL_D, in da9063_wdt_update_timeout()
101 ret = da9063_wdt_update_timeout(da9063, wdd->timeout); in da9063_wdt_start()
103 dev_err(da9063->dev, "Watchdog failed to start (err = %d)\n", in da9063_wdt_start()
116 dev_alert(da9063->dev, "Watchdog failed to stop (err = %d)\n", in da9063_wdt_stop()
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H A Dsbc8360.c1 // SPDX-License-Identifier: GPL-2.0+
15 * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
25 * "AS-IS" and at no charge.
29 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
66 * The following describes how the timer should be programmed (according to
76 * MOV AX,000nH (set multiplier n, from 1-4)
79 * MOV AX,000mH (set base timer m, from 0-F)
96 * --|----------------------------------
198 MODULE_PARM_DESC(timeout, "Index into timeout table (0-63) (default=27 (60s))");
208 /* Activate and pre-configure watchdog */
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dvga.c29 if (device->card_type >= NV_50) in nvkm_rdport()
40 if (device->card_type < NV_40) in nvkm_rdport()
51 if (device->card_type >= NV_50) in nvkm_wrport()
62 if (device->card_type < NV_40) in nvkm_wrport()
132 if (device->card_type < NV_50) in nvkm_lockvgac()
136 if (device->chipset == 0x11) { in nvkm_lockvgac()
150 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
153 * b) in tied mode (4) head B is programmed to the values set on head A, and
164 if (device->card_type < NV_50) { in nvkm_rdvgaowner()
165 if (device->chipset == 0x11) { in nvkm_rdvgaowner()
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/linux/include/net/libeth/
H A Drx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (C) 2024-2025 Intel Corporation */
18 /* Maximum headroom for worst-case calculations */
22 /* Maximum supported L2-L4 header length */
25 /* Always use order-0 pages */
29 /* HW-writeable space in one buffer: truesize - headroom/tailroom, aligned */
35 * struct libeth_fqe - structure representing an Rx buffer (fill queue element)
40 * Depending on the MTU, API switches between one-page-per-frame and shared
41 * page model (to conserve memory on bigger-page platforms). In case of the
51 * enum libeth_fqe_type - enum representing types of Rx buffers
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/linux/drivers/power/supply/
H A Dbd99954-charger.c1 // SPDX-License-Identifier: GPL-2.0-only
20 * a) Trickle-charge with constant current (8).
21 * b) pre-charge with constant current (6)
22 * c) fast-charge, first with constant current (5) phase. After
30 *(4)` `.` ` ` ` ` ` ` ` ` ` ` ` ` ` ----------------------------.
32 * . o----+/:/ ` ` ` ` ` ` ` ` ` ` ` ` `.` ` (5)
34 * . + /- -- .
35 * . +`/- + .
36 * . o/- -: .
38 * . .--+ `/ .
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/linux/include/linux/
H A Dphylink.h24 MLO_AN_FIXED, /* Fixed-link mode */
25 MLO_AN_INBAND, /* In-band protocol */
28 * PHYLINK_PCS_NEG_NONE - protocol has no inband capability
29 * PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
30 * PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
31 * 1000base-X with autoneg off
32 * PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
34 * PHYLINK_PCS_NEG_INBAND - inband mode selected
35 * PHYLINK_PCS_NEG_ENABLED - negotiation mode enabled
105 * struct phylink_link_state - link state structure
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/linux/drivers/clk/samsung/
H A Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
37 #include <linux/clk-provider.h>
40 #include "clk-cpu.h"
48 * struct exynos_cpuclk_regs - Register offsets for CPU related clocks
71 * struct exynos_cpuclk_chip - Chip specific data for CPU clock
83 * struct exynos_cpuclk - information about clock supplied to a CPU core
94 * @chip: chip-specific data for the CPU clock
111 /* ---- Common code --------------------------------------------------------- */
156 pr_err("%s: re-parenting mux timed-out\n", __func__); in wait_until_mux_stable()
162 * dividers to be programmed.
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/linux/Documentation/networking/
H A Dswitchdev.rst1 .. SPDX-License-Identifier: GPL-2.0
11 Copyright |copy| 2014-2015 Scott Feldman <sfeldma@gmail.com>
14 The Ethernet switch device driver model (switchdev) is an in-kernel driver
19 an example setup using a data-center-class switch ASIC chip. Other setups
20 with SR-IOV or soft switches, such as OVS, are possible.
25 User-space tools
28 +-------------------------------------------------------------------+
31 +--------------+-------------------------------+
35 +----------------------------------------------+
41 +--+----+----+----+----+----+---+ +-----+-----+
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/linux/Documentation/scsi/
H A DChangeLog.ncr53c8xx1 Sat May 12 12:00 2001 Gerard Roudier (groudier@club-internet.fr)
2 * version ncr53c8xx-3.4.3b
3 - Ensure LEDC bit in GPCNTL is cleared when reading the NVRAM.
4 Fix sent by Stig Telfer <stig@api-networks.com>.
5 - Define scsi_set_pci_device() as nil for kernel < 2.4.4.
7 Mon Feb 12 22:30 2001 Gerard Roudier (groudier@club-internet.fr)
8 * version ncr53c8xx-3.4.3
9 - Call pci_enable_device() as AC wants this to be done.
10 - Get both the BAR cookies actual and PCI BAR values.
12 - Merge changes for linux-2.4 that declare the host template
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/linux/drivers/net/wireless/ath/ath12k/wifi7/
H A Dhal_rx_desc.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
282 * field in address search failure cache-only entry should
286 * If set, intra-BSS routing detection is enabled
290 * and use a programmed value corresponding to the REO2PPE
304 * buffer management for WiFi-to-PPE routing.
307 * by a different subsystem, completely disabling WiFi-to-PPE
374 * Meta data that SW has programmed in the Peer table entry
517 * received MPDU in the PPDU and this MPDU gets filtered-in,
526 * Received frame was part of an A-MPDU.
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/linux/drivers/soundwire/
H A Dbus.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
24 bus->id = rc; in sdw_get_id()
26 if (bus->controller_id == -1) in sdw_get_id()
27 bus->controller_id = rc; in sdw_get_id()
33 * sdw_bus_master_add() - add a bus Master instance
49 return -ENODEV; in sdw_bus_master_add()
58 ida_init(&bus->slave_ida); in sdw_bus_master_add()
63 bus->link_id); in sdw_bus_master_add()
67 if (!bus->ops) { in sdw_bus_master_add()
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/linux/drivers/thermal/tegra/
H A Dsoctherm.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra114-soctherm.h>
35 #include <dt-bindings/thermal/tegra124-soctherm.h>
198 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
201 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
204 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
206 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
213 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
230 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
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/linux/Documentation/hwmon/
H A Dasc7621.rst20 Andigilog has both the PECI and pre-PECI versions of the Heceta-6, as
21 Intel calls them. Heceta-6e has high frequency PWM and Heceta-6p has
23 Heceta-6e part and aSC7621 is the Heceta-6p part. They are both in
28 have used registers below 20h for vendor-specific functions in addition
29 to those in the Intel-specified vendor range.
32 The fan speed control uses this finer value to produce a "step-less" fan
33 PWM output. These two bytes are "read-locked" to guarantee that once a
34 high or low byte is read, the other byte is locked-in until after the
37 sheet says 10-bits of resolution, although you may find the lower bits
47 We offer GPIO features on the former VID pins. These are open-drain
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