pre\-fetchable (full) in projects: freebsd

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Searched +full:pre +full:- +full:fetchable (Results 1 – 5 of 5) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/pci/
H A D	v3-v360epc-pci.txt	6 - compatible: should be one of: 7 "v3,v360epc-pci" 8 "arm,integrator-ap-pci", "v3,v360epc-pci" 9 - reg: should contain two register areas: 12 - interrupts: should contain a reference to the V3 error interrupt 14 - bus-range: see pci.txt 15 - ranges: this follows the standard PCI bindings in the IEEE Std 16 1275-1994 (see pci.txt) with the following restriction: 17 - The non-prefetchable and prefetchable memory windows must 19 - The prefetchable memory window must be immediately adjacent [all …]
H A D	faraday,ftpci100.yaml	1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Linus Walleij <linus.walleij@linaro.org> 21 The plain variant has 128MiB of non-prefetchable memory space, whereas the 27 and should point to respective interrupt in that controller in its interrupt-map. 29 The code which is the only documentation of how the Faraday PCI (the non-dual 34 interrupt-map-mask = <0xf800 0 0 7>; 35 interrupt-map = 54 - $ref: /schemas/pci/pci-host-bridge.yaml# [all …]
H A D	faraday,ftpci100.txt	`14 - compatible: ranging from specific to generic, should be one of 15 "cortina,gemini-pci", "faraday,ftpci100" 16 "cortina,gemini-pci-dual", "faraday,ftpci100-dual" 18 "faraday,ftpci100-dual" 19 - reg: memory base and size for the host bridge 20 - #address-cells: set to <3> 21 - #size-cells: set to <2> 22 - #interrupt-cells: set to <1> 23 - bus-range: set to <0x00 0xff> 24 - device_type, set to "pci" [all …]`
/freebsd/crypto/openssl/apps/
H A D	req.c	`2 * Copyright 1995-2024 The OpenSSL Project Authors. All Rights Reserved. 47 #define UNSET_DAYS -2 /* -1 may be used for testing expiration checks */ 48 #define EXT_COPY_UNSET -1 100 {"help", OPT_HELP, '-', "Display this summary"}, 107 {"inform", OPT_INFORM, 'F', "Input format - DER or PEM"}, 108 {"verify", OPT_VERIFY, '-', "Verify self-signature on the request"}, 111 {"new", OPT_NEW, '-', "New request"}, 114 {"utf8", OPT_UTF8, '-', "Inpu [all...]`
/freebsd/sys/dev/qlnx/qlnxe/
H A D	reg_addr.h	2 * Copyright (c) 2017-2018 Cavium, Inc. 78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl… 79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea… 80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn… 81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea… 88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of … 90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… 116 … (0x1<<9) // Fast back-to-back transaction ena… 128 … (0x1<<23) // Fast back-to-back capable. Not ap… 145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E… [all …]