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/freebsd/sys/dev/clk/rockchip/
H A Drk3568_pmucru.c77 PLIST(sclk_uart0_div_p) = { "ppll", "usb480m", "cpll", "gpll" };
88 PLIST(clk_pdpmu_p) = { "ppll", "gpll" };
101 FFACT(0, "ppll_ph0", "ppll", 1, 2),
102 FFACT(0, "ppll_ph180", "ppll", 1, 2),
106 RK_PLL(PLL_PPLL, "ppll", mux_pll_p, 0, 0),
H A Drk3399_pmucru.c760 PLIST(xin24m_ppll_p) = {"xin24m", "ppll"};
764 static struct rk_clk_pll_def ppll = { variable
767 .name = "ppll",
782 .clk.pll = &ppll
786 CDIV(PCLK_PMU_SRC, "pclk_pmu_src", "ppll", 0, 0, 0, 5),
799 CDIV(0, "clk_i2c0_div", "ppll", 0, 2, 0, 7),
801 CDIV(0, "clk_i2c8_div", "ppll", 0, 2, 8, 7),
805 CDIV(0, "clk_i2c4_div", "ppll", 0, 3, 0, 7),
H A Drk3399_cru.c706 PLIST(pll_src_cpll_gpll_ppll_p) = {"cpll", "gpll", "ppll"};
710 PLIST(pll_src_cpll_gpll_npll_ppll_p) = {"cpll", "gpll", "npll", "ppll" };
713 PLIST(pll_src_ppll_cpll_gpll_npll_upll_p) = { "ppll", "cpll", "gpll", "npll", "upll" };
715 PLIST(pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll", "ppll", "upll", "xin24m"…
H A Drk3568_cru.c269 PLIST(clk_mac_2top_p) = { "clk_cpll_div_125m", "clk_cpll_div_50m", "clk_cpll_div_25m", "ppll" };
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dimx35-clock.yaml21 ppll 2
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dxlnx-versal-clk.h19 #define PPLL 10 macro