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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dsamsung,usb3-drd-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
15 For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
18 0 - UTMI+ type phy,
19 1 - PIPE3 type phy.
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controller
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/freebsd/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,exynos-hdmi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
18 - samsung,exynos4210-hdmi
19 - samsung,exynos4212-hdmi
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H A Dsamsung,exynos-mixer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-mixe
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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddpll.txt4 register-mapped DPLL with usually two selectable input clocks
8 modes (locked, low power stop etc.) This binding has several
9 sub-types, which effectively result in slightly different setup
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible : shall be one of:
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
14 /** @brief output of gate CLK_ENB_ADSP */
16 /** @brief output of gate CLK_ENB_ADSPNEON */
20 /** @brief output of gate CLK_ENB_APB2APE */
30 /** @brief output of gate CLK_ENB_CAN1_HOST */
34 /** @brief output of gate CLK_ENB_CAN2_HOST */
46 /** @brief output of gate CLK_ENB_DPAUX */
78 * throughput and memory controller power.
85 /** @brief output of gate CLK_ENB_EQOS_RX */
[all …]
H A Dhi6220-clock.h1 /* SPDX-License-Identifier: GPL-2.0-only */
41 /* gate clocks */
60 /* gate clock */
124 /* gate clock */
130 /* gate clocks */
161 /* clk in Hi6220 power controller */
162 /* gate clocks */
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dimx8qxp-lpcg.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock
10 - Aisheng Dong <aisheng.dong@nxp.com>
13 The Low-Power Clock Gate (LPCG) modules contain a local programming
15 is used to locally gate the clocks for the associated peripheral.
24 include/dt-bindings/clock/imx8-lpcg.h
29 - const: fsl,imx8qxp-lpcg
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/freebsd/sys/contrib/device-tree/Bindings/iio/gyroscope/
H A Dinvensense,mpu3050.txt1 Invensense MPU-3050 Gyroscope device tree bindings
4 - compatible : should be "invensense,mpu3050"
5 - reg : the I2C address of the sensor
8 - interrupts : interrupt mapping for the trigger interrupt from the
13 - vdd-supply : supply regulator for the main power voltage.
14 - vlogic-supply : supply regulator for the signal voltage.
15 - mount-matrix : see iio/mount-matrix.txt
18 - The MPU-3050 will pass through and forward the I2C signals from the
21 i2c gate node. For details see: i2c/i2c-gate.txt
28 interrupt-parent = <&foo>;
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dhisilicon-histb-pcie.txt6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 "hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
16 "rc-dbi": configuration space of PCIe controller;
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
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/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxbb-wetek.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "meson-gxbb.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
19 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
30 led-power {
31 /* red in suspend or power-off */
35 default-state = "on";
36 panic-indicator;
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H A Dmeson-gxl-s905x-p212.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on meson-gx-p23x-q20x.dtsi:
5 * - Copyright (c) 2016 Endless Computers, Inc.
7 * - Copyright (c) 2016 BayLibre, SAS.
13 #include "meson-gxl-s905x.dtsi"
22 stdout-path = "serial0:115200n8";
30 hdmi_5v: regulator-hdmi-5v {
31 compatible = "regulator-fixed";
33 regulator-name = "HDMI_5V";
34 regulator-min-microvolt = <5000000>;
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H A Dmeson-gxl-s905x-nexbox-a95x.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxl-s905x.dtsi"
13 compatible = "nexbox,a95x", "amlogic,s905x", "amlogic,meson-gxl";
22 stdout-path = "serial0:115200n8";
30 vddio_card: gpio-regulator {
31 compatible = "regulator-gpio";
33 regulator-name = "VDDIO_CARD";
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <3300000>;
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H A Dmeson-gxbb-p20x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "meson-gxbb.dtsi"
17 stdout-path = "serial0:115200n8";
25 usb_pwr: regulator-usb-pwrs {
26 compatible = "regulator-fixed";
28 regulator-name = "USB_PWR";
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
35 enable-active-high;
38 vddio_card: gpio-regulator {
[all …]
H A Dmeson-gxl-s905w-jethome-jethub-j80.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
10 /dts-v1/;
12 #include "meson-gxl.dtsi"
15 compatible = "jethome,jethub-j80", "amlogic,s905w", "amlogic,meson-gxl";
22 reserved-memory {
37 stdout-path = "serial0:115200n8";
40 vddio_ao18: regulator-vddio-ao18 {
41 compatible = "regulator-fixed";
42 regulator-name = "VDDIO_AO18";
43 regulator-min-microvolt = <1800000>;
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H A Dmeson-gxm-khadas-vim2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxm.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/meson-aiu.h>
15 compatible = "khadas,vim2", "amlogic,s912", "amlogic,meson-gxm";
24 stdout-path = "serial0:115200n8";
32 adc-keys {
33 compatible = "adc-keys";
34 io-channels = <&saradc 0>;
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/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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/freebsd/sys/contrib/device-tree/src/arm/intel/pxa/
H A Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
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/freebsd/sys/contrib/device-tree/Bindings/soc/zte/
H A Dpd-2967xx.txt1 * ZTE zx2967 family Power Domains
3 zx2967 family includes support for multiple power domains which are used
4 to gate power to one or more peripherals on the processor.
7 - compatible: should be one of the following.
8 * zte,zx296718-pcu - for zx296718 power domain.
9 - reg: physical base address of the controller and length of memory mapped
11 - #power-domain-cells: Must be 1.
16 compatible = "zte,zx296718-pcu";
18 #power-domain-cells = <1>;
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap34xx-omap36xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <1>;
19 #clock-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 aes1_ick: clock-aes1-ick@3 {
25 #clock-cells = <0>;
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H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
9 #clock-cells = <0>;
10 compatible = "fixed-factor-clock";
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
18 compatible = "fixed-factor-clock";
20 clock-mult = <1>;
21 clock-div = <5>;
26 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/ux500/
H A Dpower_domain.txt1 * ST-Ericsson UX500 PM Domains
3 UX500 supports multiple PM domains which are used to gate power to one or
12 - compatible: Must be "stericsson,ux500-pm-domains".
13 - #power-domain-cells : Number of cells in a power domain specifier, must be 1.
17 compatible = "stericsson,ux500-pm-domains";
18 #power-domain-cells = <1>;
24 - power-domains: A phandle and PM domain specifier. Below are the list of
28 ----- ---------
34 power-domains = <&pm_domains DOMAIN_VAPE>
/freebsd/sys/contrib/device-tree/Bindings/power/
H A Dpd-samsung.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/pd-samsung.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Power Domains
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 Exynos processors include support for multiple power domains which are used
14 to gate power to one or more peripherals on the processor.
17 - $ref: power-domain.yaml#
22 - samsung,exynos4210-pd
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/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dmaxim,max96714.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
11 - Julien Massot <julien.massot@collabora.com>
15 CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located serializer using industry-standard coax or STP
30 - const: maxim,max96714f
31 - items:
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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbi
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