| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | st,sta350.txt | 7 - compatible: "st,sta350"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
22 - st,output-conf: number, Selects the output configuration:
23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
[all …]
|
| H A D | cs35l33.txt | 5 - compatible : "cirrus,cs35l33"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
15 - reset-gpios : gpio used to reset the amplifier
17 - interrupts : IRQ line info CS35L33.
18 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
21 - cirrus,boost-ctl : Booster voltage use to supply the amp. If the value is
26 - cirrus,ramp-rate : On power up, it affects the time from when the power
27 up sequence begins to the time the audio reaches a full-scale output.
28 On power down, it affects the time from when the power-down sequence
[all …]
|
| H A D | st,sta32x.txt | 7 - compatible: "st,sta32x"
8 - reg: the I2C address of the device for I2C
9 - reset-gpios: a GPIO spec for the reset pin. If specified, it will be
12 - power-down-gpios: a GPIO spec for the power down pin. If specified,
16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
22 - clocks, clock-names: Clock specifier for XTI input clock.
24 and disabled when it is removed. The 'clock-names' must be set to 'xti'.
26 - st,output-conf: number, Selects the output configuration:
[all …]
|
| /linux/Documentation/arch/arm/ |
| H A D | cluster-pm-race-avoidance.rst | 2 Cluster-wide Power-up/power-down race avoidance algorithm
16 ---------
20 power consumption and thermal dissipation.
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
[all …]
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| /linux/sound/soc/codecs/ |
| H A D | ssm2602.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
81 #define APDIGI_DE_EMPHASIS 0x006 /* De-Emphasis Control …
85 /*Power Down Control (SSM2602_REG_POWER)
88 #define PWR_LINE_IN_PDN 0x001 /* Line Input Power Down …
89 #define PWR_MIC_PDN 0x002 /* Microphone Input & Bias Power Down …
90 #define PWR_ADC_PDN 0x004 /* ADC Power Down …
91 #define PWR_DAC_PDN 0x008 /* DAC Power Down …
92 #define PWR_OUT_PDN 0x010 /* Outputs Power Down …
93 #define PWR_OSC_PDN 0x020 /* Oscillator Power Down …
94 #define PWR_CLK_OUT_PDN 0x040 /* CLKOUT Power Down …
[all …]
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| /linux/include/soc/at91/ |
| H A D | sama7-ddr.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
33 #define DDR3PHY_ACIOCR_CSPDD_CS0 (1 << 18) /* CS#[0] Power Down Driver */
34 #define DDR3PHY_ACIOCR_CKPDD_CK0 (1 << 8) /* CK[0] Power Down Driver */
35 #define DDR3PHY_ACIORC_ACPDD (1 << 3) /* AC Power Down Driver */
38 #define DDR3PHY_DXCCR_DXPDR (1 << 3) /* Data Power Down Receiver */
41 #define DDR3PHY_DSGCR_ODTPDD_ODT0 (1 << 20) /* ODT[0] Power Down Driver */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
45 #define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
46 #define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
47 #define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
[all …]
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3588-jaguar-pre-ict-tester.dtso | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
5 * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine
8 * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary
10 * as 2-lane CSI).
12 * This adapter routes some GPIOs to power rails and loops together some other
19 /dts-v1/;
22 #include <dt-bindings/gpio/gpio.h>
23 #include <dt-bindings/pinctrl/rockchip.h>
26 pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 {
27 compatible = "regulator-fixed";
[all …]
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| /linux/include/sound/ac97/ |
| H A D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+
33 /* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */
44 /* range 0x3c-0x58 - MODEM */
59 /* range 0x5a-0x7b - Vendor Specific */
62 /* range 0x60-0x6f (page 1) - extended codec registers */
108 #define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */
109 #define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */
110 #define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */
112 #define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */
113 #define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */
[all …]
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| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
[all …]
|
| /linux/arch/sparc/kernel/ |
| H A D | leon_pmc.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* leon_pmc.c: LEON Power-down cpu_idle() handler
15 /* List of Systems that need fixup instructions around power-down instruction */
44 /* Prepare an address to a non-cachable region. APB is always in pmc_leon_idle_fixup()
45 * none-cachable. One instruction is executed after the Sleep in pmc_leon_idle_fixup()
47 * value by accessing a non-cachable area, also we make sure the in pmc_leon_idle_fixup()
73 /* For systems without power-down, this will be no-op */ in pmc_leon_idle()
79 /* Install LEON Power Down function */
83 /* Assign power management IDLE handler */ in leon_pmc_install()
89 printk(KERN_INFO "leon: power management initialized\n"); in leon_pmc_install()
|
| /linux/Documentation/devicetree/bindings/mfd/ |
| H A D | max77620.txt | 1 MAX77620 Power management IC from Maxim Semiconductor.
4 -------------------
5 - compatible: Must be one of
9 - reg: I2C device address.
12 -------------------
13 - interrupts: The interrupt on the parent the controller is
15 - interrupt-controller: Marks the device node as an interrupt controller.
16 - #interrupt-cells: is <2> and their usage is compliant to the 2 cells
17 variant of <../interrupt-controller/interrupts.txt>
19 are defined at dt-bindings/mfd/max77620.h.
[all …]
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| /linux/arch/arm/boot/dts/qcom/ |
| H A D | qcom-apq8060-dragonboard.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/leds/common.h>
5 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
7 #include "qcom-msm8660.dtsi"
12 compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
19 stdout-path = "serial0:115200n8";
22 /* Main power of the board: 3.7V */
[all …]
|
| /linux/drivers/gpu/drm/armada/ |
| H A D | armada_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
88 /* LCD_CFG_RDREG4F - Armada 510 only */
197 CFG_PDWN1920x32 = 1 << 8, /* Armada 510: power down vscale ram */
198 CFG_PDWN256x32 = 1 << 7, /* power down cursor */
199 CFG_PDWN256x24 = 1 << 6, /* power down palette */
200 CFG_PDWN256x8 = 1 << 5, /* power down gamma */
201 CFG_PDWNHWC = 1 << 4, /* Armada 510: power down all hwc ram */
202 CFG_PDWN32x32 = 1 << 3, /* power down slave->smart ram */
203 CFG_PDWN16x66 = 1 << 2, /* power down UV fifo */
204 CFG_PDWN32x66 = 1 << 1, /* power down Y fifo */
[all …]
|
| /linux/Documentation/userspace-api/ |
| H A D | dcdbas.rst | 10 management interrupts and host control actions (system power cycle or
11 power off after OS shutdown) on certain Dell systems.
29 buffer must reside in 32-bit address space, and the physical address of the
55 to perform a power cycle or power off of the system after the OS has finished
56 shutting down. On some Dell systems, this host control feature requires that
57 a driver perform a SMI after the OS has finished shutting down.
60 to schedule the driver to perform a power cycle or power off host control
61 action after the system has finished shutting down:
67 Dell OpenManage performs the following steps to execute a power cycle or
68 power off host control action using this driver:
[all …]
|
| /linux/arch/arm/include/asm/ |
| H A D | mcpm.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright: (C) 2012-2013 Linaro Limited
40 * branch once it is ready to re-enter the kernel using ptr, or NULL if it
55 * CPU/cluster power operations API for higher subsystems to use.
59 * mcpm_is_available - returns whether MCPM is initialized and available
66 * mcpm_cpu_power_up - make given CPU in given cluster runable
72 * down then it is brought up as well, taking care not to let the other CPUs
87 * mcpm_cpu_power_down - power the calling CPU down
89 * The calling CPU is powered down.
92 * then the cluster is prepared for power-down too.
[all …]
|
| /linux/arch/arm/mach-exynos/ |
| H A D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
5 // Cloned from linux/arch/arm/mach-vexpress/platsmp.c
17 #include <linux/soc/samsung/exynos-regs-pmu.h>
29 /* XXX exynos_pen_release is cargo culted code - DO NOT COPY XXX */
30 volatile int exynos_pen_release = -1;
70 * having been woken up - this shouldn't happen in platform_do_lowpower()
72 * Just note it happening - when we're woken, we can report in platform_do_lowpower()
81 * exynos_cpu_power_down() - power down the specified cpu
82 * @cpu: the cpu to power down
[all …]
|
| /linux/include/uapi/linux/ |
| H A D | pmu.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * which controls battery charging and system power on PowerBook 3400
18 #define PMU_POWER_CTRL0 0x10 /* control power of some devices */
19 #define PMU_POWER_CTRL 0x11 /* control power of some devices */
21 #define PMU_ADB_POLL_OFF 0x21 /* disable ADB auto-poll */
23 #define PMU_WRITE_NVRAM 0x33 /* write non-volatile RAM */
25 #define PMU_READ_NVRAM 0x3b /* read non-volatile RAM */
26 #define PMU_SET_RTC 0x30 /* set real-time clock */
27 #define PMU_READ_RTC 0x38 /* read real-time clock */
28 #define PMU_SET_VOLBUTTON 0x40 /* set volume up/down position */
[all …]
|
| /linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | pinctrl-max77620.txt | 1 Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.
6 Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
11 --------------------------
14 - pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
15 - pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
16 <pinctrl-bindings.txt>.
19 sub-node have following properties:
22 ------------------
23 - pins: List of pins. Valid values of pins properties are:
27 -------------------
[all …]
|
| /linux/drivers/net/wireless/intel/iwlegacy/ |
| H A D | csr.h | 8 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
69 * whenever platform supplies power to device, even when device is in
70 * low power states due to driver-invoked device resets
71 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
86 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
100 * 31-8: Reserved
101 * 7-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
102 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
[all …]
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| /linux/drivers/usb/mtu3/ |
| H A D | mtu3_host.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * mtu3_dr.c - dual role switch and host glue layer
65 * ip-sleep wakeup mode:
66 * all clocks can be turn off, but power domain should be kept on
72 switch (ssusb->uwk_vers) { in ssusb_wakeup_ip_sleep_set()
74 reg = ssusb->uwk_reg_base + PERI_WK_CTRL1; in ssusb_wakeup_ip_sleep_set()
79 reg = ssusb->uwk_reg_base + PERI_WK_CTRL0; in ssusb_wakeup_ip_sleep_set()
84 reg = ssusb->uwk_reg_base + PERI_WK_CTRL0; in ssusb_wakeup_ip_sleep_set()
89 reg = ssusb->uwk_reg_base + PERI_WK_CTRL1_8195; in ssusb_wakeup_ip_sleep_set()
94 reg = ssusb->uwk_reg_base + PERI_WK_CTRL0_8195; in ssusb_wakeup_ip_sleep_set()
[all …]
|
| /linux/Documentation/input/devices/ |
| H A D | joystick-parport.rst | 3 .. _joystick-parport:
9 :Copyright: |copy| 1998-2000 Vojtech Pavlik <vojtech@ucw.cz>
10 :Copyright: |copy| 1998 Andree Borrmann <a.borrmann@tu-bs.de>
18 Any information in this file is provided as-is, without any guarantee that
36 Many console and 8-bit computer gamepads and joysticks are supported. The
40 ------------
57 The main problem with PC parallel ports is that they don't have +5V power
58 source on any of their pins. So, if you want a reliable source of power
59 for your pads, use either keyboard or joystick port, and make a pass-through
60 cable. You can also pull the power directly from the power supply (the red
[all …]
|
| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | nvidia,tegra20-sdhci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
23 - enum:
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
[all …]
|
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | ti-phy.txt | 6 - compatible: Should be one of
7 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
8 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
12 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
15 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
17 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
19 - reg : register ranges as listed in the reg-names property
20 - reg-names: "otghs_control" for control-phy-otghs
21 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
[all …]
|
| /linux/Documentation/trace/coresight/ |
| H A D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
13 debug module and it is mainly used for two modes: self-hosted debug and
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
29 --------------
31 - During driver registration, it uses EDDEVID and EDDEVID1 - two device ID
32 registers to decide if sample-based profiling is implemented or not. On some
36 - At the time this documentation was written, the debug driver mainly relies on
[all …]
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| /linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/ |
| H A D | rf.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
16 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); in rtl92d_phy_enable_anotherphy()
21 bool bresult = true; /* true: need to enable BB/RF power */ in rtl92d_phy_enable_anotherphy()
23 rtlhal->during_mac0init_radiob = false; in rtl92d_phy_enable_anotherphy()
24 rtlhal->during_mac1init_radioa = false; in rtl92d_phy_enable_anotherphy()
30 /* Enable BB and RF power */ in rtl92d_phy_enable_anotherphy()
47 struct rtl_hal *rtlhal = &(rtlpriv->rtlhal); in rtl92d_phy_powerdown_anotherphy()
53 rtlhal->during_mac0init_radiob = false; in rtl92d_phy_powerdown_anotherphy()
54 rtlhal->during_mac1init_radioa = false; in rtl92d_phy_powerdown_anotherphy()
[all …]
|