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/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mm-vpu-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
15 located in the VPU domain of the SoC.
20 - const: fsl,imx8mm-vpu-blk-ctrl
[all …]
H A Dfsl,imx8mq-vpu-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
15 located in the VPU domain of the SoC.
20 - const: fsl,imx8mq-vpu-blk-ctrl
[all …]
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
[all …]
H A Dfsl,imx8mp-hdmi-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hdmi-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HDMI blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HDMMI blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display pipeline
15 peripherals located in the HDMI domain of the SoC.
20 - const: fsl,imx8mp-hdmi-blk-ctrl
[all …]
H A Dfsl,imx8mp-media-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-media-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Elder <paul.elder@ideasonboard.com>
13 The i.MX8MP Media Block Control (MEDIA BLK_CTRL) is a top-level peripheral
14 providing access to the NoC and ensuring proper power sequencing of the
15 peripherals within the MEDIAMIX domain.
20 - const: fsl,imx8mp-media-blk-ctrl
21 - const: syscon
[all …]
H A Dfsl,imx8mm-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
15 peripherals located in the DISP domain of the SoC.
20 - const: fsl,imx8mm-disp-blk-ctrl
[all …]
H A Dfsl,imx8mn-disp-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MN DISP blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MN DISP blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
15 peripherals located in the DISP domain of the SoC.
20 - const: fsl,imx8mn-disp-blk-ctrl
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,sc7180-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7180-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sc7180-adsp-pas
20 - qcom,sc7180-mpss-pas
21 - qcom,sc7280-adsp-pas
22 - qcom,sc7280-cdsp-pas
23 - qcom,sc7280-mpss-pas
[all …]
H A Dqcom,sm6350-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6350-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sm6350-adsp-pas
20 - qcom,sm6350-cdsp-pas
21 - qcom,sm6350-mpss-pas
28 - description: XO clock
30 clock-names:
[all …]
H A Dqcom,sa8775p-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sa8775p-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
19 - items:
20 - enum:
21 - qcom,qcs8300-adsp-pas
22 - const: qcom,sa8775p-adsp-pas
23 - items:
[all …]
H A Dxlnx,zynqmp-r5fss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ben Levinsky <ben.levinsky@amd.com>
11 - Tanmay Shah <tanmay.shah@amd.com>
14 The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
15 real-time processing based on the Cortex-R5F processor core from ARM.
16 The Cortex-R5F processor implements the Arm v7-R architecture and includes a
17 floating-point unit that implements the Arm VFPv3 instruction set.
[all …]
H A Dqcom,sm8150-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm8150-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - items:
20 - enum:
21 - qcom,qcs615-adsp-pas
22 - const: qcom,sm8150-adsp-pas
23 - items:
[all …]
H A Dqcom,sm6375-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sm6375-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sm6375-adsp-pas
20 - qcom,sm6375-cdsp-pas
21 - qcom,sm6375-mpss-pas
28 - description: XO clock
30 clock-names:
[all …]
H A Dqcom,sc8280xp-pas.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/qcom,sc8280xp-pas.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
19 - qcom,sc8280xp-adsp-pas
20 - qcom,sc8280xp-nsp0-pas
21 - qcom,sc8280xp-nsp1-pas
28 - description: XO clock
30 clock-names:
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dfsl,imx8-acm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
19 - fsl,imx8dxl-acm
20 - fsl,imx8qm-acm
21 - fsl,imx8qxp-acm
26 power-domains:
30 '#clock-cells':
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
33 compatible = "mediatek,mt8167-apmixedsys", "syscon";
[all …]
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/clock/qcom,rpmh.h>
7 #include <dt-bindings/clock/qcom,sm4450-camcc.h>
8 #include <dt-bindings/clock/qcom,sm4450-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm4450-gcc.h>
10 #include <dt-bindings/clock/qcom,sm4450-gpucc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom,rpmhpd.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
[all …]
H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,camcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
12 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
13 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
14 #include <dt-bindings/clock/qcom,rpmh.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
[all …]
H A Dsm6115.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
7 #include <dt-bindings/clock/qcom,gcc-sm6115.h>
8 #include <dt-bindings/clock/qcom,sm6115-dispcc.h>
9 #include <dt-bindings/clock/qcom,sm6115-gpucc.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/dma/qcom-gpi.h>
12 #include <dt-bindings/firmware/qcom,scm.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
[all …]
/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-gr3d.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-gr3d.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^gr3d@[0-9a-f]+$"
19 - nvidia,tegra20-gr3d
20 - nvidia,tegra30-gr3d
21 - nvidia,tegra114-gr3d
[all …]
/linux/Documentation/devicetree/bindings/power/
H A Dpower_domain.txt4 used for power gating of selected IP blocks for power saving by reduced leakage
7 This device tree binding can be used to bind PM domain consumer devices with
8 their PM domains provided by PM domain providers. A PM domain provider can be
11 phandle arguments (so called PM domain specifiers) of length specified by the
12 #power-domain-cells property in the PM domain provider node.
14 ==PM domain providers==
16 See power-domain.yaml.
18 ==PM domain consumers==
21 - power-domains : A list of PM domain specifiers, as defined by bindings of
22 the power controller that is the PM domain provider.
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpsc.txt1 Binding for TI DaVinci Power Sleep Controller (PSC)
3 The PSC provides power management, clock gating and reset functionality. It is
7 - compatible: shall be one of:
8 - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
9 - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
10 - reg: physical base address and size of the controller's register area
11 - #clock-cells: from common clock binding; shall be set to 1
12 - #power-domain-cells: from generic power domain binding; shall be set to 1.
13 - clocks: phandles to clocks corresponding to the clock-names property
14 - clock-names: list of parent clock names - depends on compatible value
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dqcom,ssc-block-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Srba <Michael.Srba@seznam.cz>
13 This binding describes the dependencies (clocks, resets, power domains) which
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
32 - description: SSCAON_CONFIG0 registers
33 - description: SSCAON_CONFIG1 registers
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
23 - nvidia,tegra186-xudc # For Tegra186
[all …]

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