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/freebsd/sys/contrib/device-tree/src/arm64/apple/
H A Ds8001-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S8001 "A9X" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt8103-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8103 "M1" SoC
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
[all …]
H A Dt8112-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8112 "M2" SoC
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
16 apple,always-on; /* Core device */
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8112-pmgr-pwrstate", "apple,pmgr-pwrstate";
22 #power-domain-cells = <0>;
[all …]
H A Dt8011-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8011 "A10X" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt8015-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8015 "A11" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Ds5l8960x-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S5L8960X "A7" SoC
9 ps_cpu0: power-controller@20000 {
10 compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@20008 {
19 compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt8012-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8012 "T2" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt8010-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T8010 "A10" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt600x-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T6001 "M1 Max" SoC
9 DIE_NODE(ps_pms_bridge): power-controller@100 {
10 compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 DIE_NODE(ps_aic): power-controller@108 {
19 compatible = "apple,t6000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt7001-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T7001 "A8X" SoC
9 ps_cpu0: power-controller@20000 {
10 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@20008 {
19 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt7000-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T7000 "A8" SoC
8 ps_cpu0: power-controller@20000 {
9 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
11 #power-domain-cells = <0>;
12 #reset-cells = <0>;
14 apple,always-on; /* Core device */
17 ps_cpu1: power-controller@20008 {
18 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
20 #power-domain-cells = <0>;
[all …]
H A Ds800-0-3-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S8000/3 "A9" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/power/
H A Drockchip,power-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Power Domains
10 - Elaine Zhang <zhangqing@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 Rockchip processors include support for multiple power domains
16 application scenarios to save power.
18 Power domains contained within power-controller node are
[all …]
H A Dmediatek,power-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Power Domains Controller
10 - MandyJH Liu <mandyjh.liu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
14 Mediatek processors include support for multiple power domains which can be
15 powered up/down by software based on different application scenes to save power.
17 IP cores belonging to a power domain should contain a 'power-domains'
[all …]
H A Dpower-domain.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/power-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rafael J. Wysocki <rafael@kernel.org>
11 - Kevin Hilman <khilman@kernel.org>
12 - Ulf Hansson <ulf.hansson@linaro.org>
16 used for power gating of selected IP blocks for power saving by reduced
25 \#power-domain-cells property in the PM domain provider node.
29 pattern: "^(power-controller|power-domain|performance-domain)([@-].*)?$"
[all …]
H A Dbrcm,bcm63xx-power.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/brcm,bcm63xx-power.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM63xx power domain driver
10 - Álvaro Fernández Rojas <noltari@gmail.com>
13 BCM6318, BCM6328, BCM6362 and BCM63268 SoCs have a power domain controller
14 to enable/disable certain components in order to save power.
19 - enum:
20 - brcm,bcm6318-power-controller
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/rockchip/
H A Dpower_domain.txt1 * Rockchip Power Domains
3 Rockchip processors include support for multiple power domains which can be
4 powered up/down by software based on different application scenes to save power.
6 Required properties for power domain controller:
7 - compatible: Should be one of the following.
8 "rockchip,px30-power-controller" - for PX30 SoCs.
9 "rockchip,rk3036-power-controller" - for RK3036 SoCs.
10 "rockchip,rk3066-power-controller" - for RK3066 SoCs.
11 "rockchip,rk3128-power-controller" - for RK3128 SoCs.
12 "rockchip,rk3188-power-controller" - for RK3188 SoCs.
[all …]
/freebsd/sys/dev/sfxge/common/
H A Defx_regs_mcdi_strs.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2018 Solarflare Communications Inc. All rights reserved.
31 * rebuild this file with "make -C doc mcdiheaders".
39 #define MC_CMD_SENSOR_CONTROLLER_TEMP_ENUM_STR "Controller temperature: degC"
41 #define MC_CMD_SENSOR_CONTROLLER_COOLING_ENUM_STR "Controller cooling: bool"
46 #define MC_CMD_SENSOR_IN_1V0_ENUM_STR "1.0v power: mV"
47 #define MC_CMD_SENSOR_IN_1V2_ENUM_STR "1.2v power: mV"
48 #define MC_CMD_SENSOR_IN_1V8_ENUM_STR "1.8v power: mV"
49 #define MC_CMD_SENSOR_IN_2V5_ENUM_STR "2.5v power: mV"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/
H A Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
27 spi-max-frequency: true
32 - enum:
34 - abb,spi-sensor
35 # Acbel fsg032 power supply
36 - acbel,fsg032
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8-ss-img.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
13 img_pxl_clk: clock-img-pxl {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
[all …]
H A Dimx8-ss-lsio.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 lsio_bus_clk: clock-lsio-bus {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <100000000>;
14 clock-output-names = "lsio_bus_clk";
18 compatible = "simple-bus";
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/apple/
H A Dapple,pmgr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC Power Manager (PMGR)
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs include PMGR blocks responsible for power management,
14 which can control various clocks, resets, power states, and
16 with sub-nodes representing individual features.
20 pattern: "^power-management@[0-9a-f]+$"
24 - enum:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/ti/
H A Dsci-pm-domain.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI-SCI generic power domain
10 - Nishanth Menon <nm@ti.com>
13 - $ref: /schemas/power/power-domain.yaml#
16 Some TI SoCs contain a system controller (like the Power Management Micro
17 Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
19 between the host processor running an OS and the system controller happens
[all …]
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dexynos5433-clock.txt3 The Exynos5433 clock controller generates and supplies clock to various
8 - compatible: should be one of the following.
9 - "samsung,exynos5433-cmu-top" - clock controller compatible for CMU_TOP
12 - "samsung,exynos5433-cmu-cpif" - clock controller compatible for CMU_CPIF
14 - "samsung,exynos5433-cmu-mif" - clock controller compatible for CMU_MIF
15 which generates clocks for DRAM Memory Controller domain.
16 - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
18 - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
20 - "samsung,exynos5433-cmu-fsys" - clock controller compatible for CMU_FSYS
22 - "samsung,exynos5433-cmu-g2d" - clock controller compatible for CMU_G2D
[all …]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Dr8a7792.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V2H (R8A77920) SoC
8 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a7792-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
[all …]

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