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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dt1042si-post.dtsi2 * T1042 Silicon/SoC Device Tree Source (post include)
35 #include "t1040si-post.dtsi"
H A Dt2080si-post.dtsi2 * T2080 Silicon/SoC Device Tree Source (post include)
35 /include/ "t2081si-post.dtsi"
38 /include/ "qoriq-sata2-0.dtsi"
40 fsl,iommu-parent = <&pamu1>;
41 fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
44 /include/ "qoriq-sata2-1.dtsi"
46 fsl,iommu-parent = <&pamu1>;
47 fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
54 #address-cells = <2>;
55 #size-cells = <2>;
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H A Db4420si-post.dtsi2 * B4420 Silicon/SoC Device Tree Source (post include)
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
43 dcsr-epu@0 {
44 compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
46 dcsr-npc {
47 compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
49 dcsr-dpaa@9000 {
50 compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
52 dcsr-ocn@11000 {
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H A Dt1024si-post.dtsi2 * T1024 Silicon/SoC Device Tree Source (post include)
35 #include "t1023si-post.dtsi"
44 #address-cells = <1>;
45 #size-cells = <1>;
50 fsl,qe-num-riscs = <1>;
51 fsl,qe-num-snums = <28>;
52 brg-frequency = <0>;
53 bus-frequency = <0>;
59 compatible = "fsl,t1024-diu", "fsl,diu";
66 qeic: interrupt-controller@80 {
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H A Dmpc8641si-post.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MPC8641 Silicon/SoC Device Tree Source (post include)
5 * Copyright 2016 Elettra-Sincrotrone Trieste S.C.p.A.
9 #address-cells = <2>;
10 #size-cells = <1>;
11 compatible = "fsl,mpc8641-localbus", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 compatible = "fsl,mpc8641-soc", "simple-bus";
20 bus-frequency = <0>;
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H A Dmpc8548si-post.dtsi2 * MPC8548 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8548-lbc", "fsl,pq3-localbus", "simple-bus";
44 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8540-pci";
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H A Dc293si-post.dtsi2 * C293 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
44 compatible = "fsl,qoriq-pcie-v2.2", "fsl,qoriq-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
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H A Dbsc9131si-post.dtsi2 * BSC9131 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
43 #address-cells = <1>;
44 #size-cells = <1>;
46 compatible = "fsl,bsc9131-immr", "simple-bus";
47 bus-frequency = <0>; // Filled out by uboot.
49 ecm-law@0 {
50 compatible = "fsl,ecm-law";
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H A Dbsc9132si-post.dtsi2 * BSC9132 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
45 compatible = "fsl,bsc9132-pcie", "fsl,qoriq-pcie-v2.2";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
56 #address-cells = <3>;
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H A Db4860si-post.dtsi2 * B4860 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4si-post.dtsi"
39 compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
45 #address-cells = <2>;
46 #size-cells = <2>;
47 fsl,iommu-parent = <&pamu0>;
51 #address-cells = <2>;
52 #size-cells = <2>;
53 cell-index = <1>;
[all …]
H A Dp1020si-post.dtsi2 * P1020/P1011 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
[all …]
H A Dp1010si-post.dtsi2 * P1010/P1014 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
44 compatible = "fsl,p1010-pcie", "fsl,qoriq-pcie-v2.3";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
55 #size-cells = <2>;
[all …]
H A Dmpc8572si-post.dtsi2 * MPC8572 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8548-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
54 #interrupt-cells = <1>;
[all …]
H A Dmpc8544si-post.dtsi2 * MPC8544 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8544-lbc", "fsl,pq3-localbus", "simple-bus";
44 compatible = "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8548-pcie";
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H A Dp2020si-post.dtsi2 * P2020/P2010 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8548-pcie";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0 255>;
49 clock-frequency = <33333333>;
55 #interrupt-cells = <1>;
[all …]
H A Dp1021si-post.dtsi2 * P1021/P1012 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2011-2012 Freescale Semiconductor Inc.
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
[all …]
H A Dp1022si-post.dtsi2 * P1022/P1013 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
39 * The localbus on the P1022 is not a simple-bus because of the eLBC
42 compatible = "fsl,p1022-elbc", "fsl,elbc";
49 compatible = "fsl,mpc8548-pcie";
51 #size-cells = <2>;
52 #address-cells = <3>;
53 bus-range = <0 255>;
54 clock-frequency = <33333333>;
[all …]
H A Dmpc8568si-post.dtsi2 * MPC8568 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
45 compatible = "fsl,mpc8540-pci";
48 bus-range = <0 0xff>;
49 #interrupt-cells = <1>;
50 #size-cells = <2>;
51 #address-cells = <3>;
57 compatible = "fsl,mpc8548-pcie";
[all …]
H A Dmpc8536si-post.dtsi2 * MPC8536 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8536-elbc", "fsl,elbc", "simple-bus";
44 compatible = "fsl,mpc8540-pci";
47 bus-range = <0 0xff>;
48 #interrupt-cells = <1>;
49 #size-cells = <2>;
50 #address-cells = <3>;
55 compatible = "fsl,mpc8548-pcie";
[all …]
H A Dmpc8569si-post.dtsi2 * MPC8569 Silicon/SoC Device Tree Source (post include)
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
56 #interrupt-cells = <1>;
[all …]
H A Dp1023si-post.dtsi2 * P1023/P1017 Silicon/SoC Device Tree Source (post include)
4 * Copyright 2011 - 2014 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 #address-cells = <2>;
52 #size-cells = <1>;
[all …]
/freebsd/sys/dev/isci/scil/
H A Dscic_sds_remote_node_context.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
61 * associated with the remote node context in the silicon. It
62 * exists to model and manage the remote node context in the silicon.
74 // ---------------------------------------------------------------------------
115 // ---------------------------------------------------------------------------
157 // ---------------------------------------------------------------------------
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/freebsd/sys/netinet/cc/
H A Dcc.h1 /*-
2 * Copyright (c) 2007-2008
4 * Copyright (c) 2009-2010 Lawrence Stewart <lstewart@freebsd.org>
11 * Research Program Fund at Community Foundation Silicon Valley.
44 * University Research Program Fund at Community Foundation Silicon Valley.
60 /* Per-netstack bits. */
91 void *cc_data; /* Per-connection private CC algorithm data. */
112 #define CCF_HYSTART_CAN_SH_CWND 0x0800 /* Can hystart when going CSS -> CA slam the cwnd */
130 * The highest order 8 bits (0x01000000 - 0x80000000) are reserved
157 * non-null pointer it is pre-allocated memory by
[all …]
/freebsd/share/man/man4/
H A Dsiftr.439 as a module at run-time, run the following command as root:
40 .Bd -literal -offset indent
49 .Bd -literal -offset indent
66 .Ss Compile-time Configuration
72 .Bd -literal -offset indent
73 CFLAGS+=-DSIFTR_IPV6
80 In the IPv4-only (default) mode, standard dotted decimal notation (e.g.
83 and standard colon-separated hex notation (see RFC 4291) is used to format IPv6
85 .Ss Run-time Configuration
89 interface to export its configuration variables to user-space.
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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Ddwc3.txt3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
10 - clock-names: list of clock names. Ideally should be "ref",
12 - clocks: list of phandle and clock specifier pairs corresponding to
13 entries in the clock-names property.
16 clocks are optional if the parent node (i.e. glue-layer) is compatible to
18 "cavium,octeon-7130-usb-uctl"
20 "samsung,exynos5250-dwusb3"
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